• 한국미생물학회:학술대회논문집
• /
• 한국미생물학회 2002년도 추계학술대회
• /
• pp.22-26
• /
• 2002

There are a number of ways in which environmental microbiology and microbial ecology will benefit from DNA micro array technology. These include community genome arrays, SSU rDNA arrays, environmental functional gene arrays, population biology arrays, and there are clearly more different applications of microarray technology that can be applied to relevant problems in environmental microbiology. Two types of the applications, bacterial identification chip and functional gene detection chip, will be presented. For the bacterial identification chip, a new approach employing random genome fragments that eliminates the disadvantages of traditional DNA-DNA hybridization is proposed to identify and type bacteria based on genomic DNA-DNA similarity. Bacterial genomes are fragmented randomly, and representative fragments are spotted on a glass slide and then hybridized to test genomes. Resulting hybridization profiles are used in statistical procedures to identify test strains. Second, the direct binding version of microarray with a different array design and hybridization scheme is proposed to quantify target genes in environmental samples. Reference DNA was employed to normalize variations in spot size and hybridization. The approach for designing quantitative microarrays and the inferred equation from this study provide a simple and convenient way to estimate the target gene concentration from the hybridization signal ratio.

• 마이크로전자및패키징학회지
• /
• 제14권2호
• /
• pp.41-47
• /
• 2007

현재 PCB기판내에 소재나 칩부품을 이용하여 커패시터나 저항을 구현하여 내장시키는 임베디드 패시브기술에 대한 연구가 많이 진행되어 지고 있다. 본 연구에서는 커패시터 용량이나 인덕터의 특성이 검증된 칩부품을 기판내 내장시켜 다이플렉서 기판을 제작하였다. $880\;MHz{\sim}960\;MHz(GSM)$영역과 $1.71\;GHz{\sim}1.88\;GHz(DCS)$영역을 나누는 회로를 구성하기 위해 1005크기의 6개 칩을 표면실장 공정과 함몰공정으로 형성시켜 Network Analyzer로 측정하여 비교하였다. chip표면실장으로 구현된 Diplexer는 GSM에서 최대 0.86 dB의 loss, DCS에서 최대 0.68 dB의 loss가 나타났다. 표면실장과 비교하였을 때 함몰공정의 Diplexer는 GSM 대역에서 약 5 dB의 추가 loss가 나타났으며 목표대역에서 0.6 GHz정도 내려갔다. 칩 전극과 기판의 도금 연결부위는 $260^{\circ}C$, 80분의 고온공정 및 $280^{\circ}C$, 10초의 솔더딥핑의 열충격 고온공정에서도 이상이 없었으며 특성의 변화도 거의 관찰되지 않았다.

• 전자공학회논문지B
• /
• 제33B권3호
• /
• pp.186-192
• /
• 1996

A modified learning rule is introduced for the implementation of feedforward artificial neural networks with on-chip learning circuitry using standard analog CMOS technology. Learning rule, is modified form the EBP (error back propagation) rule which is one of the well-known learning rules for the feedforward rtificial neural nets(FANNs). The employed MEBP ( modified EBP) rule is well - suited for the hardware implementation of FANNs with on-chip learning rule. As a ynapse circuit, a four-quadrant vector-product linear multiplier is employed, whose input/output signals are given with voltage units. Two $2{\times}2{\times}1$ FANNs are implemented with the learning circuitry. The implemented FANN circuits have been simulatied with learning test patterns using the PSPICE circuit simulator and their results show correct learning functions.

• 한국공작기계학회:학술대회논문집
• /
• 한국공작기계학회 2003년도 춘계학술대회 논문집
• /
• pp.223-228
• /
• 2003

In end milling processes, characterized by use of rotating tools, the underformed chip thickness varies periodically with the phase change of tool. In current study, as a new approach to analyse shear behaviors In the shear plane and chip-tool friction behavior chip-tool contact region during an end milling process. In this approach, an up-end milling process is transformed into an equivalent oblique cutting process. Experimental investigations for two sets of cutting tests i.e.. up-end milling and the equivalent oblique cutting test were performed to verify the presented model.

• 센서학회지
• /
• 제8권6호
• /
• pp.469-475
• /
• 1999

공작기계의 자동화 고속화에 의해 절삭 작업은 향상되고 있지만 선삭시 발생하는 연속형 고속형칩은 작업능률을 저하시킴으로 AE센서를 이용한 절삭 실험을 통하여 절삭 조건에 따른 AE 신호의 특징을 분석하고 칩과 관련된 신호특성을 분석결과 칩 형상에 가장 중요한 요인이 되는 것은 AE진폭 신호와 AE 에너지 신호였음을 확인하였으며, AE진폭 신호와 AE에너지 신호를 통계적 처리한 결과 에너지신호 보다는 진폭 신호의 첨도값이 선삭시 절삭특성을 잘 나타내 주고 있었으며, 비절삭에너지를 이용하여 절삭성능을 종합적으로 평가하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -3
• /
• pp.1428-1431
• /
• 2002

It is general opinion that the future mobile multimedia networks will use different standards and a prospective solution to this problem will be software defined radio (SDR) techniques. SDR provides the flexibility to support multiple air interfaces and signal processing functions at the same time. Especially, digital signal processors and FPGAs are widely used for implementation of these adaptive and flexible functions of a baseband modem for SDR applications. Also, it is known that the modulation schemes of OCQPSK (Orthogonal Complex QPSK) and HPSK (Hybrid PSK) are used for IMT-2000 services of cdma2000 and WCDMA, respectively. Thus, in this paper, we design and implement an OCQPSK / HPSK modem using a DSP chip of Texas Instrument's TMS320C6701. One modulation scheme is operated by adaptive selection between the two schemes and 5 physical traffic channels differentiated by orthogonal codes are implemented in one DSP chip and each channel has 1Mbps data rates and 8Mcps chip rates.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.269-274
• /
• 1999

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC＇s(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.

• 반도체디스플레이기술학회지
• /
• 제5권1호
• /
• pp.33-38
• /
• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

• IEIE Transactions on Smart Processing and Computing
• /
• 제5권2호
• /
• pp.71-76
• /
• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• 원예과학기술지
• /
• 제32권6호
• /
• pp.788-793
• /
• 2014

Vegetative propagation of walnut is difficult compared with that of other fruit and nut species. The present study assessed three methods of grafting (patch, shield, and chip) at various periods of walnut growth and with different timings of grafting in walnut. Early May was the best time for grafting, at which time the highest success rate was obtained by the patch method (96%), followed by chip-budding (75%), while shield-grafting showed the lowest efficiency (10%). Patch-grafting was also successful (75-80%) in early August and moderately successful in mid-June (51-55%), while the shield and chip methods had no success during these two times (0.00%). Patch-grafting was more efficient and also induced better callus formation and scion growth than the other two methods. The genotypes used did not affect grafting efficiency. The best results were obtained by patch-budding in both tested genotypes. The present findings show the potential value of patch-grafting in early May as a propagation method for walnut for establishment of guidelines for propagation.