• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.25-33
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• 2011

As chip operating frequency increases, there is growing concern about on-chip interconnect inductance. This paper presents a two-step inductance screening tool to select interconnects with significant inductance effects in a VLSI design. Test chips designed in different CMOS technology nodes are examined. The inductance screening results show that 0.1% of the nets in a design have inductance problems with chips running at its operating frequency, supporting the necessity of a screening process instead of adding inductance model to all the nets in the design. The increase in resistance due to geometry scaling will strongly affect the significance of inductance on delay as technology and frequency scale. Since higher frequency worsens inductance problem and geometry scaling alleviates it, inductance screening tool can provide useful guidelines to circuit designers.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.8
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• pp.443-446
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• 2004

In this paper, a multi-band ceramic chip antenna for WLAN(Wireless LAN) applications is designed. The design target is to obtain 0 dBi of coverage gain with omni directional radiation pattern. The antenna is fabricated using Low Temperature Co-fired Ceramic(LTCC) technology. The size of the chip antenna is $2.2{\times}9.65{\times}1.02$mm. The measured antenna gain is 1 dBi at 2.44 GHz and 0.5 dBi at 5.5 GHz. The omni directional radiation pattern for the two operating bands is obtained. The measured bandwidth(S11=-10 dB) are 90 MHz at 2.44 GHz and 1280 MHz at 5.5 GHz respectively

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.2
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• pp.30-36
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• 2007

In order to estimate the maximum undeformed chip thickness in grinding operation, it is necessary to obtain the successive cutting point spacing. In the past it was obtained by experiments. In this paper, the average successive cutting point spacing has been obtained using the given grinding input conditions and it is possible to estimate the maximum undeformed chip thickness without using any experimentally obtained data. The validity of the proposed analysis has been verified based on two sets of grinding scratch tests using WA and CBN grinding wheels.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• Transactions of Materials Processing
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• v.12 no.4
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• pp.358-363
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• 2003

Adiabatic shear bands have been observed in the serrated chip during high strain rate metal cutting process of medium carbon steel and titanium alloy The recent microscopic observations have shown that dynamic recrystallization occurs in the narrow adiabatic shear bands. However the conventional flow stress models such as the Zerilli-Armstrong model and the Johnson-Cook model, in general, do not predict the occurrence of dynamic recrystallization (DRX) in the shear bands and the thermal softening effects accompanied by DRX. In the present study, a strain hardening and thermal softening model is proposed to predict the adiabatic shear localized chip formation. The finite element analysis (FEA) with this proposed flow stress model shows that the temperature of the shear band during cutting process rises above 0.5Τ$_{m}$. The simulation shows that temperature rises to initiate dynamic recrystallization, dynamic recrystallization lowers the flow stress, and that adiabatic shear localized band and the serrated chip are formed. FEA is also used to predict and compare chip formations of two flow stress models in orthogonal metal cutting with AISI 1045. The predictions of the FEA agreed well with the experimental measurements.s.

• Korean Journal of Food Science and Technology
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• v.14 no.4
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• pp.364-369
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• 1982

Two varieties of potatoes, Irish cobbler and Shimabara stored for seven and nine months respectively by irradiation combined with natural low temperature (year-round temperature change:$2{\sim}17^{\circ}C)$ on a batch scale were investigated on the suitability for processing of potato chip. Nine months after storage, irradiated potatoes (Irish cobbler) tended to maintain somewhat-better texture and sensory quality than untreated in potato chip processing. Peel rate, closely related to potato chip yield, of untreated potatoes were $20{\sim}25%$ higher than those of irradiated and Agtron color determination of potato chip from both irradiated were commercially acceptable. Preservation of potatoes by irradiation combined with natural low temperature was evaluated as an alternative method of the supply for raw materials of potato chip processing in the off season in Korea.

• ETRI Journal
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• v.37 no.6
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• pp.1176-1187
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• 2015

This work proposes a highly efficient sensorless motor driver chip for various permanent-magnet synchronous motors (PMSMs) in a wide power range. The motor driver chip is composed of two important parts. The digital part is a sensorless controller consisting mainly of an angle estimation block and a speed control block. The analog part consists of a gate driver, which is able to sense the phase current of a motor. The sensorless algorithms adapted in this paper include a sliding mode observer (SMO) method that has high robust characteristics regarding parameter variations of PMSMs. Fabricated SMO chips detect back electromotive force signals. Furthermore, motor current-sensing blocks are included with a 10-bit successive approximation analog-to-digital converter and various gain current amplifiers for proper sensorless operations. Through a fabricated SMO chip, we were able to demonstrate rated powers of 32 W, 200 W, and 1,500 W.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.294-301
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• 2017

This paper presents a low power ${\Sigma}{\Delta}$ modulator for an implantable chip to acquire a bio-signal such as EEG, DBS, and EMG. In order to reduce a power consumption of the proposed fourth order modulator, two op-amps utilized for the first two integrators are reconfigured to drive the second two integrators. The KT/C noise reduction circuit in the first two integrators is employed to enhance SNR of the modulator. The proposed circuit was fabricated in a 0.18 um CMOS n-well 1 poly 6 metal process with the active chip core area of $900um{\times}800um$ and the power consumption of 830 uW. Measurement results were demonstrated to be SNDR of 76 dB, DR of 77 dB, ENOB of 12.3 bit at the input frequency of 250 Hz and the clock frequency of 256 kHz. FOM1 and FOM2 were measured to be 41 pJ/step and 142.4 dB, respectively.

• Journal of the Optical Society of Korea
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• v.7 no.1
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• pp.1-6
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• 2003

Integration and miniaturization at the systems level are key requirements for photonics applications. Here, we describe the concept of planar integration of free-space optical systems and its use as an optical interconnection technology. Two specific applications will be considered, a parallel chip-to-chip interconnect and an optical clock distribution network.