• Title/Summary/Keyword: two-bit transform

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Enhanced Multiresolution Motion Estimation Using Reduction of One-Pixel Shift (단화소 이동 감쇠를 이용한 향상된 다중해상도 움직임 예측 방법)

  • 이상민;이지범;고형화
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.9C
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    • pp.868-875
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    • 2003
  • In this paper, enhanced multiresolution motion estimation(MRME) using reduction of one-pixel shift in wavelet domain is proposed. Conventional multiresolution motion estimation using hierarchical relationship of wavelet coefficient has difficulty for accurate motion estimation due to shift-variant property by decimation process of the wavelet transform. Therefore, to overcome shift-variant property of wavelet coefficient, two level wavelet transform is performed. In order too reduce one-pixel shift on low band signal, S$_4$ band is interpolated by inserting average value. Secondly, one level wavelet transform is applied to the interpolated S$_4$ band. To estimate initial motion vector, block matching algorithm is applied to low band signal S$_{8}$. Multiresolution motion estimation is performed at the rest subbands in low level. According to the experimental results, proposed method showed 1-2dB improvement of PSNR performance at the same bit rate as well as subjective quality compared with the conventional multiresolution motion estimation(MRME) methods and full-search block matching in wavelet domain.

A study on the constitution of S box and G function in SEED-type cipher (SEED 형식 암호에서 S 박스와 G 함수 구성에 관한 연구)

  • 송홍복;조경연
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.4A
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    • pp.291-300
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    • 2002
  • In this paper, a way of constituting optimized S box and G function was suggested in the block cipher whose structure is similar to SEED, which is KOREA standard of 128-bit block cipher. S box can be formed with nonlinear function and an affine transform. Nonlinear function must be strong with differential attack and linear attack, and it consists of an inverse number over GF(2$\^$8/) which has neither a fixed point, whose input and output are the same except 0 and 1, nor an opposite flexed number, whose output is one's complement of the input. Affine transform can be constituted so that the input/output correlation can be the lowest and there can be no fixed point or opposite fixed point. G function undergoes diffusive linear transform with 4 S-box outputs using the matrix of 4$\times$4 over GF(2$\^$8/). G function can be constituted so that MDS(Maximum Distance Separable) code can be formed, SAC(Strict Avalanche Criterion) can be met, there can be no weak input, where a fried point, an opposite fried point, and output can be two's complement of input, and the construction of hardware can be made easy. The S box and G function suggested in this paper can be used as a constituent of the block cipher with high security, in that they are strong with differential attack and linear attack with no weak input and they are excellent at diffusion.

Design of Radix-4 FFT Processor Using Twice Perfect Shuffle (이중 완전 Shuffle을 이용한 Radix-4 FFT 프로세서의 설계)

  • Hwang, Myoung-Ha;Hwang, Ho-Jung
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.2
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    • pp.144-150
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    • 1990
  • This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

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Digital Watermarking of EZW Coded Image using ZTR symbol (EZW 비트열의 ZTR 심벌을 이용한 디지털 워터마킹)

  • Kim Hyun-Woo;Lee Ho-Keun;Lee Myong-Young;Ha Yeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.1
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    • pp.43-50
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    • 2005
  • We proposed a method for embedding coded binary data into EZW bitstreams and extracting embedded data from EZW bitstreams using the traditional EZW decoder. EZW coder have two passes. The first pass, the dominant pass have four symbols, P, N, IZ, ZTR. The second pass is sub-ordinary pass which specifies the value of symbol. In the proposed methods, we use ZTR symbol in the dominant pass. We embed watermark into ZTR symbol in the highest frequency band which original image is transferred by wavelet transform. The proposed digital watermarking method shows good properties for robustness in the low bit rate. Accordingly, based on the proposed digital watermarking, video and 3D image watermarking will become a new area for research in the near future.

Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec

  • Kim, Sunwoong;Jang, Ji Hun;Lee, Hyuk-Jae;Rhee, Chae Eun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.446-457
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    • 2017
  • In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

Induction Motor Bearing Damage Detection Using Stator Current Monitoring (고정자전류 모니터링에 의한 유도전동기 베어링고장 검출에 관한 연구)

  • Yoon, Chung-Sup;Hong, Won-Pyo
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.6
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    • pp.36-45
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    • 2005
  • This paper addresses the application of motor current spectral analysis for the detection of rolling-element bearing damage in induction machines. We set the experimental test bed. They is composed of the normal condition bearing system, the abnormal rolling-element bearing system of 2 type induction motors with shaft deflection system by external force and a hole drilled through the outer race of the shaft end bearing of the four pole test motor. We have developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current The effects on the stator current spectrum are described and related frequencies are also determined. This is an important result in the formulation of a fault detection scheme that monitors the stator currents. We utilized the FFT(Fast Fourier Transform), Wavelet analysis and averaging signal pattern by inner product tool to analyze stator current components. Especially, the analyzed results by inner product clearly illustrate that the stator signature analysis can be used to identify the presence of a bearing fault.

Improvement of Bandwidth Efficiency for High Transmission Capacity of Contents Streaming Data using Compressive Sensing Technique (컨텐츠 스트리밍 데이터의 전송효율 증대를 위한 압축센싱기반 전송채널 대역폭 절감기술 연구)

  • Jung, Eui-Suk;Lee, Yong-Tae;Han, Sang-Kook
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.3
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    • pp.2141-2145
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    • 2015
  • A new broadcasting signal transmission, which can save its channel bandwidth using compressive sensing(CS), is proposed in this paper. A new compression technique, which uses two dimensional discrete wavelet transform technique, is proposed to get high sparsity of multimedia image. A L1 minimization technique based on orthogonal matching pursuit is also introduced in order to reconstruct the compressed multimedia image. The CS enables us to save the channel bandwidth of wired and wireless broadcasting signal because various transmitted data are compressed using it. A $256{\times}256$ gray-scale image with compression rato of 20 %, which is sampled by 10 Gs/s, was transmitted to an optical receiver through 20-km optical transmission and then was reconstructed successfully using L1 minimization (bit error rate of $10^{-12}$ at the received optical power of -12.2 dB).

Gradual Block-based Efficient Lossy Location Coding for Image Retrieval (영상 검색을 위한 점진적 블록 크기 기반의 효율적인 손실 좌표 압축 기술)

  • Choi, Gyeongmin;Jung, Hyunil;Kim, Haekwang
    • Journal of Broadcast Engineering
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    • v.18 no.2
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    • pp.319-322
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    • 2013
  • Image retrieval research activity has moved its focus from global descriptors to local descriptors of feature point such as SIFT. MPEG is Currently working on standardization of effective coding of location and local descriptors of feature point in the context mobile based image search driven application in the name of MPEG-7 CDVS (Compact Descriptor for Visual Search). The extracted feature points consist of two parts, location information and Descriptor. For efficient image retrieval, we proposed a novel method that is gradual block-based efficient lossy location coding to compress location information according to distribution in images. From experimental result, the number of average bits per feature point reduce 5~6% and the accuracy rate keep compared to state of the art TM 3.0.

ECG-based Biometric Authentication Using Random Forest (랜덤 포레스트를 이용한 심전도 기반 생체 인증)

  • Kim, JeongKyun;Lee, Kang Bok;Hong, Sang Gi
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.6
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    • pp.100-105
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    • 2017
  • This work presents an ECG biometric recognition system for the purpose of biometric authentication. ECG biometric approaches are divided into two major categories, fiducial-based and non-fiducial-based methods. This paper proposes a new non-fiducial framework using discrete cosine transform and a Random Forest classifier. When using DCT, most of the signal information tends to be concentrated in a few low-frequency components. In order to apply feature vector of Random Forest, DCT feature vectors of ECG heartbeats are constructed by using the first 40 DCT coefficients. RF is based on the computation of a large number of decision trees. It is relatively fast, robust and inherently suitable for multi-class problems. Furthermore, it trade-off threshold between admission and rejection of ID inside RF classifier. As a result, proposed method offers 99.9% recognition rates when tested on MIT-BIH NSRDB.

Fixed-Point Modeling and Performance Analysis of a SIFT Keypoints Localization Algorithm for SoC Hardware Design (SoC 하드웨어 설계를 위한 SIFT 특징점 위치 결정 알고리즘의 고정 소수점 모델링 및 성능 분석)

  • Park, Chan-Ill;Lee, Su-Hyun;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.49-59
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    • 2008
  • SIFT(Scale Invariant Feature Transform) is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vortices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3-D image constructions, and its most computation-intensive stage is a keypoint localization. In this paper, we develope a fixed-point model of the keypoint localization and propose its efficient hardware architecture for embedded applications. The bit-length of key variables are determined based on two performance measures: localization accuracy and error rate. Comparing with the original algorithm (implemented in Matlab), the accuracy and error rate of the proposed fixed point model are 93.57% and 2.72% respectively. In addition, we found that most of missing keypoints appeared at the edges of an object which are not very important in the case of keypoints matching. We estimate that the hardware implementation will give processing speed of $10{\sim}15\;frame/sec$, while its fixed point implementation on Pentium Core2Duo (2.13 GHz) and ARM9 (400 MHz) takes 10 seconds and one hour each to process a frame.