• 제목/요약/키워드: tunneling parameters

검색결과 99건 처리시간 0.023초

Reliability analysis of tunnel face stability considering seepage effects and strength conditions

  • Park, Jun Kyung
    • Geomechanics and Engineering
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    • 제29권3호
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    • pp.331-338
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    • 2022
  • Face stability analyses provides the most probable failure mechanisms and the understanding about parameters that need to be considered for the evaluation of ground movements caused by tunneling. After the Upper Bound Method (UBM) solution which can consider the influence of seepage forces and depth-dependent effective cohesion is verified with the numerical experiments, the probabilistic model is proposed to calculate the unbiased limiting tunnel collapse pressure. A reliability analysis of a shallow circular tunnel driven by a pressurized shield in a frictional and cohesive soil is presented to consider the inherent uncertainty in the input parameters and the proposed model. The probability of failure that exceeding a specified applied pressure at the tunnel face is estimated. Sensitivity and importance measures are computed to identify the key parameters and random variables in the model.

10 nm 이하 DGMOSFET의 항복전압과 채널도핑농도의 관계 (Relation of Breakdown Voltage and Channel Doping Concentration of Sub-10 nm Double Gate MOSFET)

  • 정학기
    • 한국정보통신학회논문지
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    • 제21권6호
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    • pp.1069-1074
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    • 2017
  • 항복전압의 감소는 채널길이 감소에 의하여 발생하는 심각한 단채널 효과이다. 본 논문에서는 10 nm 이하 채널길이를 갖는 이중게이트 MOSFET에서 채널크기의 변화를 파라미터로 하여 채널도핑에 따른 항복전압의 변화를 고찰하였다. 이를 위하여 해석학적 전위분포에 의한 열방사 전류와 터널링 전류를 구하고 두 성분의 합으로 구성된 드레인 전류가 $10{\mu}A$가 될 때, 드레인 전압을 항복전압으로 정의하였다. 결과적으로 채널 도핑농도가 증가할수록 항복전압은 크게 증가하였다. 채널길이가 감소하면서 항복전압이 크게 감소하였으며 이를 해결하기 위하여 실리콘 두께 및 산화막 두께를 매우 작게 유지하여야만 한다는 것을 알 수 있었다. 특히 터널링 전류의 구성비가 증가할수록 항복전압이 증가하는 것을 관찰하였다.

싱가포르 포트캐닝 전석층에 적용된 EPBM의 설계 및 시공 (A Design and Operation of EPBM Applied in Fort Canning Boulder Bed of Singapore)

  • 김욱영;노승환;노상림
    • 터널과지하공간
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    • 제25권5호
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    • pp.417-422
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    • 2015
  • 본 논문은 TBM을 이용한 터널 굴착에서 커터의 마모 및 파손, 그에 따른 굴착속도 저하와 커터교체에 따른 공기 지연 등으로 인하여 프로젝트 전반에 심각한 영향을 미치는 전석층 지반 터널링에 관한 내용으로, 매우 조밀하고 단단한 상태의 점토지반에 강한 강도를 지니는 암석을 포함하는 싱가포르 포트캐닝 볼더베드(Fort Canning Boulder Bed, FCBB)에서의 터널링 경험을 바탕으로 볼더층을 통과하게 되는 토압식 쉴드TBM의 설계 및 시공 시 고려해야 할 주요 사항 및 볼더지반에서의 커터 마모 및 파손 특성, 점토 및 암석이 혼재된 지반에서의 쏘일 컨디셔닝 등의 내용을 기술하였으며, 향후 유사 지반에서의 터널링 프로젝트에 참고가 되길 기대한다.

터널 화재(Modified Hydrocarbon Curve)시콘크리트에 매입된 강재의 열적 손상 평가 (Evaluation on the Thermal Damage of Steel Embedded in Concrete in Tunnel Fire(Modified Hydrocarbon Curve))

  • 박경훈;김흥열;김형준
    • 한국콘크리트학회:학술대회논문집
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    • 한국콘크리트학회 2008년도 추계 학술발표회 제20권2호
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    • pp.485-488
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    • 2008
  • 터널 화재시 화재강도는 매우 높으며 터널 내부에서 화재 발생은 높은 화재강도에 의해 구조요소인 숏크리트 및 콘크리트 라이닝의 화재 노출표면에서 폭열 발생을 유발시키는 동시에 터널 안정에 있어 중요한 역할을 수행하는 앵커 등의 터널에 매입된 강재 또한 고온의 노출로 인한 열전달로 급격한 응력감소가 발생하게 된다. 따라서 본 실험에서는 화재강도(Modified Hydrocarbon Curve)와 매입된 강재의 내화 유무를 변수로 정하여 콘크리트 라이닝의 내부에 매입된 강재의 열전도를 알아보기 위한 화재시험을 수행하였다. 또한 최근 ITA(International Tunneling Association)에서 연구한 도로 터널내화구조 기준에 따라 강재의 열손상 임계 온도범위를 산정하여 열적 손상 정도를 평가하였다.

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Determination of effective parameters on surface settlement during shield TBM

  • Kim, Dongku;Pham, Khanh;Park, Sangyeong;Oh, Ju-Young;Choi, Hangseok
    • Geomechanics and Engineering
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    • 제21권2호
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    • pp.153-164
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    • 2020
  • Tunnel excavation in shallow soft ground conditions of urban areas experiences inevitable surface settlements that threaten the stability of nearby infrastructures. Surface settlements during shield TBM tunneling are related to a number of factors including geotechnical conditions, tunnel geometry and excavation methods. In this paper, a database collected from a construction section of Hong Kong subway was used to analyze the correlation of settlement-inducing factors and surface settlements monitored at different locations of a transverse trough. The Pearson correlation analysis result revealed a correlation between the factors in consideration. Factors such as the face pressure, advance speed, thrust force, cutter torque, twin tunnel distance and ground water level presented a modest correlation with the surface settlement, while no significant trends between the other factors and the surface settlements were observed. It can be concluded that an integrated effect of the settlement-inducing factors should be related to the magnitude of surface settlements.

Cell Characteristics of a Multiple Alloy Nano-Dots Memory Structure

  • Kil, Gyu-Hyun;Lee, Gae-Hun;An, Ho-Joong;Song, Yun-Heup
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.240-240
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    • 2010
  • A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

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Rigorous Design of 22-nm Node 4-Terminal SOI FinFETs for Reliable Low Standby Power Operation with Semi-empirical Parameters

  • Cho, Seong-Jae;O'uchi, Shinichi;Endo, Kazuhiko;Kim, Sang-Wan;Son, Young-Hwan;Kang, In-Man;Masahara, Meishoku;Harris, James S.Jr;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권4호
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    • pp.265-275
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    • 2010
  • In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

Numerical analysis of non-uniform segmental lining design effects on large-diameter tunnels in complex multi-layered strata

  • Joohyun Park;Seok-Jun Kang;Jun-Beom An;Gye-Chun Cho
    • Geomechanics and Engineering
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    • 제38권6호
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    • pp.553-569
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    • 2024
  • In recent tunneling projects, encounters with multi-layered strata have become more frequent as the desired scale of tunneling increases. Despite substantial practical experience, the design of large-diameter shield-driven tunnels often simplifies the surrounding ground as uniform, overlooking the complexities introduced by non-uniform geotechnical factors. This study comparatively analyzed the influence of design factors, particularly segment stiffness and joint parameters, on segmental lining behavior in layered ground conditions using numerical methods. A comprehensive parametric study revealed the significant impact of deformative interaction between the lining and the soft top soil layer on overall tunnel behavior. Permitting lining deformation in the soft soil layer effectively mitigated the induced internal forces but resulted in considerable tunnel lining convergence, adopting a peanut-shaped appearance. From a practical design perspective, application of a soft segment with lower stiffness near the stiff soil layer is an economically advantageous approach, alleviating internal forces within an acceptable convergence level. Notably, around the interfaces between soil layers with different stiffnesses, the induced internal forces in the lining were minimized based on joint rotational stiffness and location. This indicates the possibility of achieving an optimal design for segmental lining joints under layered ground conditions. Additionally, a preliminary design method was proposed, which sequentially optimizes parameters for joints located near soil layer interfaces. Subsequently, a specialized design based on the proposed method for complex multi-layered strata was compared with a conventional design. The results confirmed that the internal force was effectively relieved at an allowable lining deflection level.

Single-Electron Pass-Transistor Logic with Multiple Tunnel Junctions and Its Hybrid Circuit with MOSFETs

  • Cho, Young-Kyun;Jeong, Yoon-Ha
    • ETRI Journal
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    • 제26권6호
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    • pp.669-672
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    • 2004
  • To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters $C_g=C_T=C_{clk}=1\;aF,\;R_T=5\;M{\Omega},\;V_{clk}=40\;mV$, and $V_{in}=20\;mV$. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.

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A Compact Quantum Model for Cylindrical Surrounding Gate MOSFETs using High-k Dielectrics

  • Vimala, P.;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • 제9권2호
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    • pp.649-654
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    • 2014
  • In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.