• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.751-754
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• 2008

본 연구에서는 나노구조 FinFET 제작시 게이트산화막 특성이 서브문턱영역에서 전송특성에 미치는 영향을 분석하고자 한다. 이를 위하여 분석학적 전송모델을 사용하였으며 분석학적 모델을 유도하기 위하여 포아슨방정식을 이용하였다. 나노구조 FinFET에서 문턱전압이하의 전류전도에 영향을 미치는 열방사전류와 터널링전류에 대하여 분석하였으며 본 연구의 모델이 타당하다는 것을 입증하기 위하여 서브문턱스윙값을 이차원 시뮬레이션값과 비교하였다. 결과적으로 본 연구에서 제시한 전송특성모델이 이차원 시뮬레이션모델과 매우 잘 일치하였으며 FinFET의 전송특성이 게이트산화막의 특성에 따라 매우 큰 변화를 보이는 것을 알 수 있었다. 특히 게이트길이가 작아지면서 전송특성에 커다란 영향을 미치는 터널링특성에 대하여 집중적으로 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.129-130
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• 2009

The P/E characteristics of $HfO_2$ CTF memory capacitor with $SiO_2/HfO_2/Al_2O_3$(OHA) engineered tunnel barrier were investigated. After a growth of thermal oxide with a thickness of 2 nm, 1 nm $HfO_2$ and 3 $Al_2O_3$ layers were deposited by atomic layer deposition (ALD) system. The band offset was calculated by analysis of conduction mechanisms through Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. Moreover the PIE characteristics of $HfO_2$ CTF memory capacitor with OHA tunnel barrier was presented.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.832-834
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• 1992

Using the PECVD method, the silicon nitride films were deposited by changing the $SiH_4/NH_3$ gas flow ratio from 0.2 to 1.4 at an interval of 0.2, AES, FTIR, and Spectroscopic Ellipsomter were used to analyze the film composition and structure, the refractive index, and the deposition rate. Also the C-V analysis was used to estimate the memory performance in the capacitor type MNOS memory devices, which utilized native oxide as the tunneling barrier, with the silicon nitride by the above deposition conditions. As a result, it was confirmed that the performance of MNOS memory devices with PECVD silicon nitride was comparable to that with LPCVD or APCVD silion nitride.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Progress in Superconductivity
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• v.3 no.1
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• pp.49-55
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• 2001

Josephson junction arrays were fabricated by DC magnetron sputtering, self-aligning and reactive ion etching technique. The Al native oxide, formed by thermal oxidation, was used as the tunneling barrier of Nb/$Al-A1_2$$O_3$Nb trilayer. The arrays have 2,000 Josephson junctions with the area of $14\mu\textrm{m}$ $\times$ $46\mu\textrm{m}$. The gap voltages were in the range of 2.5 ~2.6 mV and the spread of critical current was $\pm$11~14%. When operated at 70~94 ㎓, the arrays generated zero-crossing steps up to 2.1~2.4 V. To improve transmission of microwave power and prevent diffusion of oxygen into Nb ground-plane while depositing $SiO_2$dielectric, we applied a plasma nitridation process to the Nb ground-plane. The microwave power was well propagated in Josephson junction arrays with nitridation. The difference in microwave transmission 7an be interpreted by the surface impedance change depending on nitridation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.127-128
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• 2008

The electrical characteristics of VARIOT (variable oxide thickness) with various $HfO_2$ thicknesses on thin $SiO_2$ or $Al_2O_3$ layer were investigated. Especially, the charge trapping characteristics of $HfO_2$ layer were intensively studied. The thin $HfO_2$ layer has small charge trapping characteristics while the thick $HfO_2$ layer has large memory window. Therefore, the $HfO_2$ layer is superior material and can be applied to charge storage as well as tunneling barrier of the non-volatile memory applications.