• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.897-904
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• 2011

In this paper, a novel circuit topology of a low-noise amplifier tunable at 1.8GHz band for PCS and 2.4GHz band for WLAN using a CMOS active inductor is proposed. This circuit topology to reduce higher noise figure of the low noise amplifier with the CMOS active load is analyzed. Furthermore, the noise canceling technique is adopted to reduce more the noise figure. The noise figure of the proposed circuit topology is analyzed and simulated in $0.18{\mu}m$ CMOS process technology. Thus, the simulation results exhibit that the noise performance enhancement of the tunable low noise amplifier is about 3.4dB, which is mainly due to the proposed new circuit topology.

• ETRI Journal
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• v.36 no.3
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• pp.510-513
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• 2014

A Q-band pHEMT image-rejection low-noise amplifier (IR-LNA) is presented using inter-stage tunable resonators. The inter-stage L-C resonators can maximize an image rejection by functioning as inter-stage matching circuits at an operating frequency ($F_{OP}$) and short circuits at an image frequency ($F_{IM}$). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L-C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR-LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and $F_{IM}/F_{OP}$ of the reported millimeter/quasi-millimeter wave IR-LNAs.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.264-265
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• 2007

In this paper, we deal with a hybrid dual band low noise amplifier with tunable matching circuits for a Radio Frequency Identification(RFID) reader operating at 433MHz and 912MHz. The tunable matching circuit consists of the microstrip line, SMD component and varactor. Simulation results show that the S21 parameter is 17dB and 7.91dB at 433MHz and 912MHz, respectively. The noise figure is also determined to 3.56dB and 5.58dB at the same frequencies with a power consumption of 19.36mW.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.3-6
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• 2007

In this paper, a hybrid dual band LNA(Low Noise Amplifier) with a tunable matching circuit using varactor is designed for 433MHz and 912MHz RFID reader. The operating frequency is controlled by the bias voltage applied to the varactor. The measured results demonstrate that S21 parameter is 16.01dB and 10.72dB at 433MHz and 912MHz, respectively with a power consumption of 19.36mW. The S11 are -11.88dB and -3.31dB, the S22 are -11.18dB and -15.02dB at the same frequencies. The measured NF (Noise Figure) is 15.96dB and 7.21dB at 433MHz and 912MHz, respectively. The NF had poorer performance than the simulation results. The reason for this discrepancy was thought that the input matching is not performed exactly and a varactor in the input matching circuit degrades the NF characteristics.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.17-24
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• 2014

In this paper, we propose a CMOS FM RX front-end structure with an automatic tunable input matching network and implement it using a 65nm CMOS technology. The proposed FM RX front-end is designed to change the resonance frequency of the input matching network at the low noise amplifier (LNA) according to the channel frequency selected by a phase-locked loop (PLL) for maintaining almost constant sensitivity level when an embedded antenna type with high frequency selectivity characteristic is used for FM receiver. The simulation results of implemented FM front-end show about 38dB of voltage gain, below 2.5dB of noise figure, and -15.5dBm of input referred intercept point (IIP3) respectively, while drawing only 3.5mA from 1.8V supply voltage including an LO buffer.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• ETRI Journal
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• v.23 no.1
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• pp.1-8
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• 2001

The performance of a long wavelength-band erbium-doped fiber amplifier (L-band EDFA) using 1530nm-band pumping has been studied. A 1530nm-band pump source is built using a tunable light source and two C-band EDFAs in cascaded configuration, which is able to deliver a maximum output power of 23dBm. Gain coefficient and noise figure (NF) of the L-band EDFA are measured for pump wavelengths between 1530nm and 1560nm. The gain coefficient with a 1545nm pump is more than twice as large as with a 1480nm pump. It indicates that the L-band EDFA consumes low power. The noise figure of 1530nm pump is 6.36dB at worst, which is 0.75dB higher than that of 1480nm pumped EDFA. The optimum pump wavelength range to obtain high gain and low NF in the 1530nm band appears to be between 1530nm and 1540nm. Gain spectra as a function of a pump wavelength have bandwidth of more than 10nm so that a broadband pump source can be used as 1530nm-band pump. The L-band EDFA is also tested for WDM signals. Flat Gain bandwidth is 32nm from 1571.5 to 1603.5nm within 1dB excursion at input signal of -10dBm/ch. These results demonstrate that 1530nm-band pump can be used as a new efficient pump source for L-band EDFAs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1249-1255
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• 2008

1530nm band has been studied as pump wavelength for long-wavelength-band erbium-doped fiber amplifier (L-band EDFA). The pump source is built using a tunable light source and cascaded conventional-band (C-band) EDFA. The L-band EDFA uses a forward pumping scheme. Within the 1530nm band, 1545nm pump demonstrates 0.45dB/mW gain coefficient, which is twice better than that of conventional 1480nm pumped EDFA. The noise figure of 1530nm pump is at worst 6.36dB, which is 0.75dB higher than that of 1480nm pumped EDFA. Such high gain coefficient indicates that the L-band EDFA consumes low power.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.