• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.12
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• pp.1174-1180
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• 2011

Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.776-780
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• 2007

In this paper, the charge pump circuit of a VPP generator for a low voltage DRAM is newly proposed. The proposed charge pump is a 2-stage cross coupled charge pump circuit. The charge transfer efficiency is improved, and Distributed Clock Inverter is located in each charge pump stage to reduce clock period so that the pumping current is increased. In addition, the precharge circuit is located at Gate node of charge transfer transistor to solve the problem which is that the Gate node is maintained high voltage because the boosted charge can't discharge, so device reliability is decreased. The simulation result is that pumping current, pumping efficiency and power efficiency is improved. The layout of the proposed VPP generator is designed using $0.18{\mu}m$ Triple-Well process.

• Progress in Medical Physics
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• v.20 no.2
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• pp.72-79
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• 2009

Scatter correction for I-131 plays a very important role to improve image quality and quantitation. I-131 has multiple and higher energy gamma-ray emissions. Image quality and quantitative accuracy in I-131 imaging are degraded by object scatter as well as scatter and septal penetration in the collimator. The purpose of this study was to estimate scatter and septal penetration and investigate two scatter correction methods using Monte Carlo simulation. The gamma camera system simulated in this study was a FORTE system (Phillips, Nederland) with high energy, general-purpose, parallel hole collimator. We simulated for two types of high energy collimators. One is composed of lead, and the other is composed of artificially high Z number and high density. We simulated energy spectrum using a point source in air. We estimated both full width at half maximum (FWHM) and full width at tenth maximum (FWTM) using line spread function (LSF) in cylindrical water phantom. We applied two scatter correction methods, triple energy window scatter correction (TEW) and extended triple energy window scatter correction (ETEW). The TEW method is a pixel-by pixel based correction which is easy to implement clinically. The ETEW is a modification of the TEW which corrects for scatter by using abutted scatter rejection window, which can overestimate or the underestimate scatter. The both FWHM and FWTM were estimated as 41.2 mm and 206.5 mm for lead collimator, respectively. The FWHM and FWTM were estimated as 27.3 mm and 45.6 mm for artificially high Z and high density collimator, respectively. ETEW showed that the estimation of scatter components was close to the true scatter components. In conclusion, correction for septal penetration and scatter is important to improve image quality and quantitative accuracy in I-131 imaging. The ETEW method in scatter correction appeared to be useful in I-131 imaging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.18-24
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• 2002

n this paper, we have fabricated pseudomorphic high electron mobility transistors (PHEMT) with a 0.2 ${\mu}{\textrm}{m}$ wide-head T-shaped gate using electron beam lithography by a dose split method. To make the T-shape gate with gate length of 0.2 ${\mu}{\textrm}{m}$ and gate head size of 1.3 ${\mu}{\textrm}{m}$ we have used triple layer resist structure of PMMA/P(MMA-MAA)/PMMA. The DC characteristics of PHEMT, which has 0.2 ${\mu}{\textrm}{m}$ of gate length, 80 ${\mu}{\textrm}{m}$ of unit gate width and 4 gate fingers, are drain current density of 323 ㎃/mm and maximum transconductance 232 mS/mm at $V_{gs}$ = -1.2V and $V_{ds}$ = 3V. The RF characteristics of the same device are 2.91㏈ of S21 gain and 11.42㏈ of MAG at 40GHz. The current gain cut-off frequency is 63GHz and maximum oscillation frequency is 150GHz, respectively.ively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.248-248
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• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.

• ETRI Journal
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• v.30 no.2
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• pp.308-314
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• 2008

In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

• Electrical & Electronic Materials
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• v.7 no.2
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• pp.123-129
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• 1994

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.717-720
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• 2007

We fabricated the 3.5 inch QCIF AMOLED panel with ultra low temperature polycrystalline silicon TFT on the plastic substrate. To reduce the leakage current, we used the triple layered gate metal structure. To reduce the stress from inorganic dielectric layer, we applied the organic interlayer dielectric and the photoactive insulating layer. By using the interlayer dielectric as a capacitor, the mask steps are reduced up to five.