• Title/Summary/Keyword: trench-MOS

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The Study of Improving Forward Blocking Characteristics for Small Sized Lateral Trench Electrode Power MOSFET using Trench Isolation (수평형 파워 MOSFET에 있어서 트렌치 Isolation 적용에 의한 순방향 항복특성 개선을 위한 새로운 소자의 설계에 관한 연구)

  • Kim, Jin-Ho;Kim, Je-Yoon;Ryu, Jang-Woo;Sung, Man-Young;Kim, Ki-Nam
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.9-12
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    • 2004
  • In this paper, a new small sized Lateral Trench Electrode Power MOS was proposed. This new structure, called LTEMOS(Lateral Trench Electrode Power MOS), was based on the conventional lateral power MOS. But the entire electrodes of LTEMOS were placed in trench oxide. The forward blocking voltage of the proposed LTEMOS was improved by 1.5 times with that of the conventional lateral power MOS. The forward blocking voltage of LTEMOS was about 240 V. At the same size, an improvement of the forward blocking voltage of about 1.5 times relative to the conventional MOS was observed by using ISE-TCAD which was used for analyzing device's electrical characteristics. Because all of the electrodes of the proposed device were formed in each trench oxide, the electric field was crowded to trench oxide and punch-through breakdown was occurred, lately.

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Design and Numerical Analyses of SOI Trench-MOS Bipolar-Mode Field Effect Transistor (SOI 트렌치-모스 바이폴라-모드 전계효과 트랜지스터 구조의 설계 및 수치해석)

  • Kim, Du-Yeong;O, Jae-Geun;Han, Min-Gu;Choe, Yeon-Ik
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.5
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    • pp.270-277
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    • 2000
  • A new Lateral Trench-MOS Bipolar-Mode Field-Effect Transistor(LTMBMFET) is proposed and verified by MEDICI simulation. By using a trench MOS structure, the proposed device can enhance the current gain without sacrificing other device characteristics such as the breakdown voltage. The channel region of the proposed device is formed between the trench MOS structure. So the effect of the substrate voltage is negligible when compared with the conventional device which has a channel region between the gate junction and the buried oxide layer.

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Modified Trench MOS Barrier Schottky (TMBS) Rectifier

  • Moon Jin-Woo;Choi Yearn-Ik;Chung Sang-Koo
    • KIEE International Transactions on Electrophysics and Applications
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    • v.5C no.2
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    • pp.58-62
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    • 2005
  • A trench MOS barrier Schottky (TMBS) rectifier is proposed which utilizes the upper half of the trench sidewall as an active area. The proposed structure improves the forward voltage drop by 20$\%$ in comparison with the conventional one without degradation in breakdown voltage. An analytical model for the field distribution is given and compared with two-dimensional numerical simulations.

A 4H-SiC Trench MOS Barrier Schottky (TMBS) Rectifier using the trapezoid mesa and the upper half of sidewall (Trapezoid mesa와 Half Sidewall Technique을 이용한 4H-SiC Trench MOS Barrier Schottky(TMBS) Rectifier)

  • Kim, Byung-Soo;Kim, Kwang-Soo
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.428-433
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    • 2013
  • In this study, an 4H-SiC Trench MOS Barrier Schottky (TMBS) rectifier which utilizes the trapezoid mesa structure and the upper half of the trench sidewall is proposed to improve the forward voltage drop and reverse blocking voltage concurrently. The proposed 4H-SiC TMBS rectifier reduces the forward voltage drop by 12% compared to the conventional 4H-SiC TMBS rectifier with the tilted sidewall and improves the reverse blocking voltage by 11% with adjusting the length of the upper sidewall. The Silvaco T-CAD was used to analyze the electrical characteristics.

Trench D-MOS using MicroTec oxide according to the size of the current - voltage characteristics (MicroTec을 이용한 Trench D-MOS의 산화막크기에 따른 전류-전압 특성)

  • Lim, Se-Hoon;Han, Ji-Hyeong;Jung, Hak-Kee;Lee, Jong-In;Cheong, Dong-Soo;Kwon, Oh-Sin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.779-781
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    • 2010
  • Trench D-MOS(double-diffusion MOS)는 기존의 D-MOS를 대체한 것으로 전체 전류의 길이를 짧게 함으로써 온전압강하가 낮아지게 된다. 따라서 소자가 턴-온시에 전력소모가 작게 되며, 온저항과 트레이드 오프관계인 턴-오프 특성도 그다지 나빠지지 않아 트레이드 오프 특성도 개선되어지는 장점이 있다. 본 논문은 MicoroTec 시뮬레이션을 이용하여 Trench D-MOS의 산화벽을 다르게하여 전류-전압 특성을 연구하였다.

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The Study for Investigation of the sufficient vertical profile with reducing loading effect for silicon deep trench etching (Vertical Profile Silicon Deep Trench Etch와 Loading effect의 최소화에 대한 연구)

  • Kim, Sang-Yong;Jeong, Woo-Yang;Yi, Keun-Man;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.118-119
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    • 2009
  • This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

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A Study on the 1,700 V Rated NPT Trench IGBT Analysis by PIN Diode - PNP Transistor Model (PIN 다이오드 - PNP 트랜지스터 결합모델에 의한 1,700 V급 NPT 트랜치 IGBT의 해석에 관한 연구)

  • Lee, Jong-Seok;Kyoung, Sin-Su;Kang, Ey-Goo;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.10
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    • pp.889-895
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    • 2008
  • This paper presents a comprehensive mathematical analysis and simulation of trench IGBT with the help of PIN-PNP combinational model. Since trench IGBT is characteristically influenced by PIN diode, it may be almost impossible to analyze the trench IGBT using PNP-MOS modeling methods, even PIN-MOS techniques which neglect the hole current components coming into p-base region. A new PIN-PNP complementary cooperational model is developed in order to make up the drawbacks of existing models. It would allow us to make qualitative analysis as well as simulation about switching and on-state characteristics of 1,700 V trench IGBT. Moreover, if we improve the PIN diode effects through the optimization of trench structure, trench IGBT is expected to be one of the most promising devices in the not only high-voltage but also high speed switching device field.

Optimal Design of Field Ring for Power Devices (고 내압 전력 소자 설계를 위한 필드 링 최적화에 관한 연구)

  • Kang, Ey-Goo
    • Journal of IKEEE
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    • v.14 no.3
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    • pp.199-204
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    • 2010
  • In this paper, we proposed trench field ring for breakdown voltage of power devices. The proposed trench field ring was improved 10% efficiency comparing with conventional field ring. we analyzed five parameters of trench field ring for design of trench field ring and carried out 2-D devices simulation and process simulations. That is, we analyzed number of field ring, juction depth, distance of field rings, trench width, doping profield. The proposed trench field ring was better to more 1000V.

Trends of Power Semiconductor Device (전력 반도체의 개발 동향)

  • Yun, Chong-Man
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.3-6
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    • 2004
  • Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

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A Design of Lateral Power MOS with Improved Blocking Characteristics (향상된 항복특성을 위한 수평형 파워 MOS의 설계)

  • Kim, Dae-Jong;Sung, Man-Young;Kang, Ey-Goo
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 2003.11a
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    • pp.95-98
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    • 2003
  • Power semiconductors are being currently used as a application of intelligent power inverters to a refrigerator, a washing machine and a vacuum cleaner as well as core parts of industrial system. The rating of semiconductor devices is an important factor in decision on the field of application and the forward blocking voltage is one of factors in decision of the rating. The Power MOS device has a merit of high input impedance, short switching time, and stability in temperature as well known. Power MOS devices are mainly used as switches in the field of power electronics, especially the on-state resistance and breakdown voltage are regarded as the most important parameters. Power MOS devices that enable a small size, a light weight, high-integration and relatively high voltage are required these days. In this paper, we proposed the new lateral power MOS which has forward blocking voltage of 250V and contains trench electrodes and verified manufactural possibility by using TSUPREM-4 that is process simulator.

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