• Title/Summary/Keyword: transmission line pulse

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Measurement and Analysis of Transient Voltage for an Inverter-fed Induction Motor (인버터 구동 유도전동기에서 과도전압의 측정과 분석)

  • Kil, Gyung-Suk;Rhyu, Keel-Soo;Park, Dae-Won;Cho, Young-Jin;Cheon, Sang-Gyu;Choi, Su-Yeon
    • Journal of the Korean Society for Railway
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    • v.10 no.6
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    • pp.650-654
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    • 2007
  • Induction motors are widely used as a source of driving force in electric vehicles and pulse width modulation (PWM) inverters are applied to their operation. The issue is that insulation of inverter-fed induction motors (IFMs) are more stressed than in line-powered motors by transient voltages. This paper dealt with experimental results on transient voltage produced by the PWM operation of an induction motor. The peak and the dv/dt of transient voltage depending on the length of power feeding cable and operating frequency were investigated. In the experiment, transient voltages up to 3.3PU of the rated-inverter voltage were recorded for the cable length of 50m. As the cable length is increased, the peak voltage appeared at the motor terminals increases. This phenomenon can be explained by the reflection and the transmission of travelling wave. Consequently, special care for the cable length between the motor and the inverter should be taken in the use of IFM to ensure the full life of insulation system.

Compensation of Chromatic Dispersion and Self Phase Modulation in Long-haul Optical Transmission System using Mid-span Optical Phase Conjugator (Mid-span Optical Phase Conjugator를 이용한 장거리 광 전송 시스템에서의 색 분산과 자기 위상 변조의 보상에 관한 연구)

  • 이성렬;이윤현
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.4
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    • pp.576-585
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    • 2001
  • In this paper, we investigated the method of compensation for optical pulse shape distortion due to both chromatic dispersion and SPM(self phase modulation) in a single mode fiber We selected MSSI(mid-span spectral inversion) as compensation method using OPC(optical phase conjugator). We used EOP(eye-opening penalty) parameter in order to evaluate the efficiency of waveform distortion compensation. In this paper, we induced optimum pump power level in optical phase conjugator through analytic method of computer simulation. And we investigated input signal power range being able to maintain stable reception performance under the condition of optimum pump power. We verified the possibility of high performance optical transmission system realization through the inducement and application of optimum pump power, input signal power and in-line amplifier spacing, because power control is important in the compensation for optical pulse distortion.

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Transient Response of Optically-Controlled Microwave Pulse through Open-Ended Microstrip Lines

  • Kim, Yong K.;Kim, Jin-Su;Park, Kyoung-Su
    • KIEE International Transactions on Electrophysics and Applications
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    • v.4C no.5
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    • pp.236-240
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    • 2004
  • In this paper we examine the reflection characteristics of dielectric microstrip lines with open-ended termination containing an optically induced plasma region, which are analyzed by the assumption that the plasma is distributed homogeneously in laser illumination. The characteristics impedances resulting from the presence of plasma are evaluated by the transmission line model. To estimate theoretically the characteristic response of identical systems in the time domain, the Fourier transformation method is evaluated. The reflection characteristics of time and frequency response in microwave systems have been calculated using an equivalent circuit model.

Analysis of the LIGBT-based ESD Protection Circuit with Latch-up Immunity and High Robustness (래치-업 면역과 높은 감내 특성을 가지는 LIGBT 기반 ESD 보호회로에 대한 연구)

  • Kwak, Jae Chang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.11
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    • pp.686-689
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    • 2014
  • Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

Study of Dynamic Characteristics of an UPFC Switching-Level Model (UPFC의 스위칭레벨 상세 모의 및 동적 특성 고찰)

  • Won, D.J.;Kim, S.H.;Han, H.G.;Lee, S.K.;Moon, S.I.
    • Proceedings of the KIEE Conference
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    • 1999.07c
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    • pp.1287-1289
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    • 1999
  • The UPFC(Unified Power Flow Controller) controls the magnitude and phase of the series injected voltage to exchange the real and reactive power with transmission line. The UPFC consists of two inverters connected together through the DC link capacitor. This paper describes the detailed UPFC switching-level model. PWM (Pulse Width Modulation) method is chosen to operate the inverters. Automatic voltage control mode and automatic power flow control mode is selected to control the UPFC. EMTP simulation is offered to obtain the basic operation characteristics of the UPFC and the dynamic characteristics of the UPFC is studied in detail.

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A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps

  • Jung, Jin-Woo;Koo, Yong-Seo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.339-344
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    • 2014
  • This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

Time Reversal Beam Focusing of Ultrasonic Array Transducer on a Defect in a Two Layer Medium

  • Jeong, Hyun-Jo;Lee, Jeong-Sik;Bae, Sung-Min
    • Journal of the Korean Society for Nondestructive Testing
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    • v.29 no.3
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    • pp.242-247
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    • 2009
  • The ability of time reversal techniques to focus ultrasonic beams on the source location is important in many aspects of ultrasonic nondestructive evaluation. In this paper, we investigate the time reversal beam focusing of ultrasonic array sensors on a defect in layered media. Numerical modeling is performed using the commercially available software which employs a time domain finite difference method. Two different time reversal approaches are considered - the through transmission and the pulse-echo. Linear array sensors composed of N elements of line sources are used for signal reception/excitation, time reversal, and reemission in time reversal processes associated with the scattering source of a side-drilled hole located in the second layer of two layer structure. The simulation results demonstrate the time reversal focusing even with multiple reflections from the interface of layered structure. We examine the focusing resolution that is related to the propagation distance, the size of array sensor and the wavelength.

Development of RSFQ Logic Circuits and Delay Time Considerations in Circuit Design (RSFQ 논리회로의 개발과 회로설계에 대한 지연시간 고려)

  • Kang, J.H.;Kim, J.Y.
    • Progress in Superconductivity
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    • v.9 no.2
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    • pp.157-161
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    • 2008
  • Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

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A Study on the Synthesis of Multivalued Logic System Using Current-Mode Techniques (전류방식기법에 의한 다치론이계의 구성에 관한 연구)

  • 한만춘;신명철;박종국;최정문;김락교;이래호
    • 전기의세계
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    • v.28 no.1
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    • pp.43-52
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    • 1979
  • Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

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Surge Voltage Distribution at the Different Bonding Practice During a Direct Lightning Stroke to Building (건물의 직격뢰시 본딩 방식에 따른 서지 진압 분포)

  • Lee, Jae-Bok;Chang, Sug-Hun;Myung, Sung-Ho;Cho, Yuen-Gue
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.57 no.4
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    • pp.444-450
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    • 2008
  • There are several ways to bond to building grounding systems for reducing GPR(ground potential rise) and EMI resulting from power system faults or lightning stroke to building. In order to verify effective bonding practice, the GPR and voltage of equipment due to the direct stroke to building are calculated with ATP-EMTP model for transformer, transmission line and MOV(Metal oxide varistor). The simulated model shows a satisfactory accuracy compared with experimental result for the $8/20{\mu}s$ simulated current pulse. It is observed that separate grounding can cause dangerous voltage to the building equipment and the performance of surge protective device can improve when it is installed to the protected equipment in distance as short as possible.