• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• Journal of the Korean Society of Radiology
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• v.13 no.6
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• pp.831-840
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• 2019

The X-ray detector by liquid crystal with front light was proposed and verified by a X-ray image. The proposed detector utilizes the visible light instead of the electric signal by transistor. Therefore, it shows low noise and can be fabricated at low cost. The liquid crystal detector uses the orientation change of the liquid crystal molecule by conductivity change of the photoconductive layer. We can get the X-ray image from the transmitted light through the liquid crystal. The X-ray dose was calibrated from the measured transmittance of the visible light after comparison to the reference transmittance curve of the liquid crystal. The amorphous Se was used for photo con ducting layer and parylene was used for the liquid crystal alignment instead of the conventional alignment layer which needs high-temperature process over 200℃. The proposed X-ray detector can decrease the X-ray dose by high sensitivity which was verified by simulation. After the fabrication of the X-ray detector, the X-ray image was obtained as a function of the bias voltage to the liquid crystal. 10 lines/mm resolution was obtained from the line pattern and we will apply it to the 17inch diagonal liquid crystal X-ray detector with 3π retardation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.169-169
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• 2010

As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

• Journal of IKEEE
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• v.25 no.3
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• pp.501-505
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• 2021

In this study, we fabricated amorphous indium-tin-gallium-zinc-oxide thin-film transistors (a-ITGZO TFTs) with gate dielectrics of HfO₂ and the mixed layers of HfO₂ and Al₂O₃, and investigated the effect of gate dielectric on electrical characteristics of a-ITGZO TFTs. When only HfO₂ was used as the gate dielectric, the mobility and subthreshold swing (SS) were 32.3 cm²/Vs and 206 mV/dec. For the a-ITGZO TFTs with gate dielectric made of HfO₂ and Al₂O (2:1, 1:1), the mobilities and SS were 26.4 cm²/Vs (2:1), 16.8 cm²/Vs(1:1), 160 mV/dec (2:1) and 173 mV/dec (1:1). On the other hand, the hysteresis window shown in transfer curves of the a-ITGZO TFTs was lessened from 0.60 to 0.09 V by the increase of Al₂O₃ ratio in gate dielectric, indicating that the interface trap density between the gate dielectric and channel layer decreases due to Al₂O₃.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.4
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• pp.282-285
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• 2019

A 100-nm gate-length metamorphic high electron mobility transistor(mHEMT) with a T-shaped gate was fabricated using a two-step gate recess and characterized for DC and microwave performance. The mHEMT device exhibited DC output characteristics having drain current($I_{dss}$), an extrinsic transconductance($g_m$) of 1,090 mS/mm and a threshold voltage($V_{th}$) of -0.65 V. The $f_T$ and $f_{max}$ obtained for the 100-nm mHEMT device were 190 and 260 GHz, respectively. The developed mHEMT will be applied in fabricating W-band monolithic microwave integrated circuits(MMICs).

• Journal of Adhesion and Interface
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• v.22 no.3
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• pp.91-97
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• 2021

By introducing an organic interlayer on the Parylene C dielectric surface, the electrical device performances and the operating stabilities of organic field-effect transistors (OFETs) were improved. To achieve this goal, hexamethyldisilazane (HMDS) and octadecyltrichlorosilane (ODTS), as the organic interlayer materials, were used to control the surface energy of the Parylene C dielectrics. For the bare case used with the pristine Parylene C dielectrics, the field-effect mobility (μ_FET) and threshold voltage (V_th) of dinaphtho[2,3-b:2',3'-f ]thieno[3,2-b]- thiophene (DNTT) FET devices were measured at 0.12 cm²V^-1s^-1 and - 5.23 V, respectively. On the other hand, the OFET devices with HMDS- and ODTS-modified cases showed the improved μ_FET values of 0.32 and 0.34 cm²V^-1s^-1, respectively. More important point is that the μ_FET and V_th of the DNTT FET device with the ODTS-modified Parylene C dielectric presented the smallest changes during a repeated measurement of 1000 times, implying that it has the most stable operating stability. The results could be meaned that the organic interlayer, especially ODTS, effectively covers the Parylene C dielectric surface with alkyl chains and reduces the charge trapping at the interface region between active layer and dielectric, thereby improving the electrical operating stability.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.3
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• pp.415-421
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• 2021

This study analyzed the effect on the cooling performance of the channel shape of a heat sink for an insulated gate bipolar transistor (IGBT). A serpentine channel was used for this analysis, and the parameter for the analysis was the number of curves. The analysis was conducted using computational fluid dynamics with the commercial software ANSYS fluent. One curve in the channel improved the heat dissipation performance of the heat sink by up to 8% compared to a straight-channel heat sink. However, two curves in the channel could not improve the heat discharge performance further. Instead, the two curves caused a higher pressure drop, which induces parasitic loss for the pumping of coolant. The pressure drop of the two-curve channel case was 2.48-2.55 times larger than that of a one-curve channel. This higher pressure drop decreased the heat discharge efficiency of the heat sink with two curves. The discharge heat per unit pressure drop was calculated, and the result of the straight heat sink was highest among the analyzed cases. This means that the heat discharge efficiency of the straight heat sink is the highest.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.