• Journal of IKEEE
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• v.11 no.3
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• pp.122-128
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• 2007

Sinusoidal voltage-controlled oscillators (VCOs) based on Colpitts and Hartley oscillators are presented. They consist of a LC parallel-tuned circuit connected in a negative-feedback loop with an OTA-R amplifier and two diode limiters, where the inductor is simulated one realized with temperature-stable linear operational transconductance amplifiers (OTAs) and a grounded capacitor. Prototype VCOs are built with discrete components. The Colpitts VCO exhibits less than 1% nonlinearity in its current-to-frequency transfer characteristic from 4.2 to 21.7 MHz and ${\pm}$95 ppm/$^{\circ}C$ temperature drift of frequency over 0 to $70^{\circ}C$. The total harmonic distortion (THD) is as low as 2.92% with a peak-to-peak amplitude of 0.7 V for a frequency-tuning range of 10.8-32 MHz. The Hartley VCO has the temperature drift and THD of two times higher than those of the Colpitts VCO.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.54-62
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• 2003

A systematic synthesis process is described lot the simulation of current-controllable inductors using operational transconductance amplifiers (OTAs). The process is used to obtain three circuits; two are believed It) be novel. The process is also applied to design current-controllable frequency-dependent negative resistances (FDNRs). Operation principles of designed circuits are presented and experimental results are used to verify theoretical predictions. The results show close agreement between predicted behavior and experimental performance. The application of a FDNR to a current-controllable band-pass filter is also presented.

• 전기의세계
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• v.30 no.10
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.1
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• pp.19-22
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• 1999

N-doped and low-hydrogenated DLC thin films were coated on the Mo-tip FEAs in order to improve the field emission performance and their electrical properties were evaluated. The fabricated devices showed improved field emission performance in terms of turn-on voltage, emission current and current fluctuation. This result might be caused both by the shift of Fermi level toward conduction band by N-doping and by the inherent stability of DLC material. Furthermore, the transconductance of the DLC-coated Mo-tip FEA and electrical conductivity and optical band-gap of the deposited DLC films were investigated.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.98-104
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• 1990

A study of the operation of surface and buried mode PMOSFET's is condusted. Using device with different channel length and channel implant dosage, threshold voltage lowering, transcon-diuctance and subthreshold characteristics of surface mode PMOFET are compared with those of buried mode MPOSFET. From the results, the surface channel device were more resistant to short channel effect than the buried channel device.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.207-210
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• 2000

This paper introduces a voltage-mode biquadratic circuit using only Operational Amplifiers (OTAs) and Operational Transconductance Amplifiers (OTAs). The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. Some examples are given together with simulated results by PSpice. The circuit configuration is very suitable for implementation in both bipolar and CMOS technologies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.486-489
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• 2002

In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.490-493
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• 2002

In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.