• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.135-141
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• 1994

A linear BiCMOS operational transconductance amplifier (OTA) is described. It consists of a CMOS linear transconductor and a bipolar translineear current gain cell followed by three CMOS current mirrors. The proposed circuit has comparable linearity and temperature stability but superior dc characteristics to its bipolar counterpart. A test circuit with a transconductance of 47.3$\mu$s has been simulated. Simulation results show that a linearity error of less than $\pm$1 percent over an input volgate range from -1.0 to 1.0 V and a output dc offset current as small as-3.6 nA can be obtained.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.875-878
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• 1999

In this paper, we measured and simulated the transconductance change of submicron LDD NMOSFETs due to back bias under various channel length, temperature and substrate doping conditions. As back bias is increased, the mobility will decrease and g$_{m}$ decreases according to a conventional model. But as the channel length is reduced, this phenomenon is inverted and g$_{m}$ increases in the submicron region. This can be explained by analyzing the electron quasi Fermi potential in the channel. And the empirical formulae which show the g$_{m}$ change were induced. These will be helpful to enhance the efficiency and precision of IC design.esign.

• ETRI Journal
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• v.35 no.2
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• pp.226-233
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• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.326-333
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• 2015

This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in $0.5-{\mu}m$ CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.789-794
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• 1986

The current-voltage characteristics of ion-implanted GaAs MESFET's have been simulated by using the velocity saturation model. Using this model, a MESFET with threshold voltage of -0.5V and transconductance of 460 mS/mm is designed. To implement high transconductance MESFET's, low energy ion-implantation (20 keV) and RTP(Rapid Thermal Process) activation ($575^{\circ}C$, 5sec) processes are required.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.259-261
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• 1999

An operational transconductance amplifier (OTA) based precision full-wave rectifier circuit is presented in this article. The proposed circuit has a very sharp corner in the DC transfer characteristic and simple configuration comprised three OTAs and one current mirror. The temperature dependence of the OTA transconductance is reduced. Experimental results demonstrating the characteristic of the circuit are included.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.64-70
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• 1995

A new DC drain-current model of GaAs MESFET with improved accuracy is proposed in this paper. The proposed model includes the decrease of current slope according to gate voltages. It is possible to represent a transconductance compression using the proposed model. It shows improved transconductance and output resistance in accuracy from the forward biased gate region to near the cutoff region. The wquaer error of saturation current is decreased by 46% compared with Statz model. The proposed model can be useful for the simulation of large-signal operation and harmonic distortion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.37-44
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• 2007

A low-voltage high-linear bipolar OTA and its application to IF bandpass filter for GSM cellular telephone are presented. The OTA consists of a low-voltage linear transconductor, a translinear current gain cell, and three current mirrors. The bandpass filter is composed of two cascaded identical second-order bandpass filters, which consist of a resistor, a capacitor, and a grounded simulated inductor realized with two OTA's and a grounded capacitor. SPICE simulations using an 8 GHz bipolar transistor-array parameter show that the OTA with a transconductance of 1 mS exhibits a linearity error of less than ${\pm}2%$ over an input voltage range of ${\pm}0.65\;V$ at supply voltages of ${\pm}2.0\;V$. Temperature coefficient of the transconductance is less than $-90ppm/^{\circ}C$. The bandpass filter has a center frequency of 85 MHz and Q-factor of 80. Temperature coefficient of the center frequency is less than $-182ppm/^{\circ}C$. The power dissipation of the filter is 128 mW.

• Journal of IKEEE
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• v.12 no.3
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• pp.167-171
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• 2008

A bridge resistance deviation-to-frequency (BRD-to-F) converter is presented for interfacing resistive sensor bridges. It consists of a linear operational transconductance amplifier (LOTA), a current-controlled oscillator (CCO). The prototype converter was simulated using commercially available discrete components. The result shows that the converter has a conversion sensitivity amounting to 16.90 kHz/${\Omega}$ and a linearity error less than ${\pm}$0.03 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.32-38
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• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.