• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.201-204
• /
• 2001

LDMOSFET devices operated at low temperature have applications on satellite, space shuttle and low temperature system, etc. In this study, we measured the electrical characteristics of 100v Class LDMOSFET for low temperature application. Measurement data are taken over a wide range of temperatures (100K-300K) and various drift region lengths(6.6${\mu}{\textrm}{m}$, 8.4${\mu}{\textrm}{m}$, 12.6${\mu}{\textrm}{m}$). Maximum transconductance, $g_{m}$ and drain current at low temperatures(~100K) increased over about 260%, 50% respectively, in comparison with the data at room temperature. Breakdown voltage B $V_{ds}$, and specific on- resistance decreased. Besides, ratio $R_{on}$ BV, a figure of merit of the device, decreased with decreasing temperature.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.189-192
• /
• 2001

We have studied fabrication processes that form asymmetric $\Gamma$-gate with a 0.1${\mu}{\textrm}{m}$ gate length in MMIC's(Monolithic Microwave Integrated Circuits). Asymmetric $\Gamma$-gate was fabricated using mixture of PMMA and MCB. Thus pseudomorphic high electron mobility transistor (PHEMT's) with 0.1${\mu}{\textrm}{m}$ gate length was fabricated via several steps such as mesa isolation, metalization, recess, passivation. PHEMT's has the -1.75 V of pinch-off voltage (Vp), 63 mA of drain saturation current(Idss and 363.6 mS/mm of maximum transconductance (Gm) in DC characteristics and current gain cut-off frequency of 106 GHz and maximum frequency of oscillation of 160 GHz in RF characteristics.

• 전자공학회논문지D
• /
• 제34D권12호
• /
• pp.69-75
• /
• 1997

A Si-channle MESFET using .delta.-doped layers was designed and the considerable enhancement of the current driving capability of the device was observed by simulation. The channel consists of double .delta.-doped layers separated by a low-doped spacer. Cariers are spilt from the .delta.-doped layers and are accumulated in the spacer. The saturation current is enhanced by the contribution of the carriers in the spacer. Among the design parameters that affect the peformance of the device, the thickness of the spacer and the ratio of the doping concentrations of the two .delta.-doped layers were studied. The spacer thickenss of 300~500.angs. and the doping ratio of 3~4 were shown to be the optimized values. The saturation current was observed to be increased by 75% compared with a bulk-channel MESFET. The performances of transconductance, output resistance, and subthreshold swing were also enhanced.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.295-298
• /
• 1999

AlGaAs/InGaAs power P-HEMTS (Pseudo-morphic High Electron Mobility Transistors) with 1.0-${\mu}{\textrm}{m}$ gate length for PCS applications have been fabricated. We adopted single heterojunction P-HEMT structure with two Si-delta doped layer to obtain higher current density. It exhibits a maximum current density of 512㎃/mm, an extrinsic transconductance of 259mS/mm, and a gate to drain breakdown voltage of 12.0V, respectively. The device exhibits a power density of 657㎽/mm, a maximum power added efficiency of 42.1%, a linear power gain of 9.85㏈ respectively at a drain bias of 6.0V, gate bias of 0.6V and an operation frequency of 1.765㎓.

• 한국광학회:학술대회논문집
• /
• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
• /
• pp.190-193
• /
• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• 대한전자공학회논문지
• /
• 제26권9호
• /
• pp.1375-1380
• /
• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.

• 전자공학회논문지A
• /
• 제29A권4호
• /
• pp.33-37
• /
• 1992

AlGaAs/GaAs quantum well delta-doped channel FET's have been successfully fabricated using by low-pressure metalorganic chemical vapor deposition(LP-MOCVD). The FET's with a gate dimension of 1.8$\mu$m $\times$ 100$\mu$m have a maximum transconductance of 190 mS/mm and a maximum current density of 425 mA/nm. The devices show extremely broad transconductances with a large voltage swing of 2.4V. The S-parameter measurements have indicated that the current gain and power gain cutoff frequencies of the device were 7 and 15 GHz, respectively. These values are among the best performance reported for GaAs based heterojunction FET's with a similar device geometry.

• 전자공학회논문지A
• /
• 제30A권9호
• /
• pp.30-37
• /
• 1993

In this paper, we present a simple and general lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and gate current influence to solve a problem that that I$_{b}$ is dependent on drain structure. The suggested model is applied to a different channel, drain structured PMOSFET. For all PMOSFETs, dg$_{m}$/g$_{m}$ of PMOSFET appears with one straight line about Q$_{g}$, therefore, this model using I$_{g}$ is consistent with experiment result independently of channel, drain structure. It is, therefore, proposed that a model using I$_{g}$ has a general applicability for PMOSFET's.

• 전자공학회논문지A
• /
• 제31A권9호
• /
• pp.72-77
• /
• 1994

GaAs MISFETs, with photo-CVD grown P$_{3}$N$_{5}$ gate insulator and sulfide treatment, have been fabricated and showed the instability of drain current reduced less than 22 percent for the period of 1.0s~1.0${\times}10^{4}s$. The effective electron mobility and extrinsic transconductance of the device are about 1300cm$^{2}$/V.sec and 1.33mS at room temperature. The C-V characteristics of GaAs MIS Diode and AES analysis are also discussed with respect to effect of sulfide treatment conditions.

• 전자공학회논문지A
• /
• 제31A권9호
• /
• pp.114-120
• /
• 1994

We have been successfully fabricated the low nois HEMT device with AlGaAs and GaAs structure. The epitazial layer with n-type AlgaAs and undoped GaAs was grown by molecular beam epitaxy(MBE) system. Ohmic resistivity of the ource and drain contact is below 5${\times}10^{6}{\Omega}{\cdot}cm^{2}$ by the rapid thermal annealing (RTA) process. The ideality factor of the Schottky gate is below 1.6 and the gate material was Ti/Pt/Au. The HEMTs with 0.25$\mu$m-long and 200$\mu$m-wide gates have exhibited a noise figure of 0.65dB with associated gain of 9dB at 12GHz, and a transconductance of 208mS/mm.