• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.81-88
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• 2007

In on-line transaction, the transparency is the key factor for the taxation and customer's rights. Using the cash register concept of the off-line transaction, we studied on-line transaction register model for the e-commerce transparency. Although on-line transaction register may be used under the related e-commerce laws, in this paper, we only considered the mechanism of the register. The register issues the digital receipt, and then the receipt can be verified the validation by the models developed in this paper.

• Journal of Convergence for Information Technology
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• v.12 no.4
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• pp.103-110
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• 2022

Online transactions are more familiar in various fields due to the development of the ICT and the increase in trading platforms. In particular, the amount of transactions is increasing due to the increase in used transaction platforms and users, and reliability is very important due to the nature of used transactions. Among them, the used car market is very active because automobiles are operated over a long period of time. However, used car transactions are a representative market to which information asymmetry is applied. In this paper presents a DID-based transaction model that guarantees reliability to solve problems with false advertisements and false sales in used car transactions. In the used car transaction model, sellers only register data issued by the issuing agency to prevent false sales at the time of initial sales registration. It is authenticated with DID Auth in the issuance process, it is safe from attacks such as sniping and middleman attacks. In the presented transaction model, integrity is verified with VP's Proof item to increase reliability and solve information asymmetry. Also, through direct transactions between buyers and sellers, there is no third-party intervention, which has the effect of reducing fees.

• Spatial Information Research
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• v.21 no.6
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• pp.69-80
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• 2013

Our country has made every efforts to develop Real Estate Transaction culture with emphasis on Licensed Realtors by introducing Real Estate Transaction Law in 1983. Also, MOLIT(Ministry of Land, Infrastructure and Transport) designated several organizations including KAR(Korea Association of Realtors) as Real Estate Transaction Information Network Licensees for data credibility enhancement and transaction transparency. Nevertheless, the level of law abiding spirit and transaction culture are still similar to those of the old 'Bokdeokbang' era. The under-developed transaction behaviors prevent the social capital of people's credibility on Licensed Realtors from advancing, and results in the outcomes of unnecessary social cost. That is, very low credibility on the data on Sales Items in the market and the fear of speculative real estate price uprise and market distortions are continuing on. In this context, the purpose of this study is to propose the model of GIS-based Modernized Real Estate Transaction System and its execution policies to support credible Real Estate Information to the general public for efficient transactions in the market. Accordingly, the study aims at contributing to the modernization of Real Estate Transactions, fostering competitiveness of Realtors in the Real Estate Market.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1653-1658
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. In this study, we compare the characteristics of various arbitration policies using TLM(Transaction Level Model) method. Fixed priority, round-robin, TDMA and Lottery bus policies are used in general arbitration method. We analyze the merit and demerit of these arbitration policies.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.6
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• pp.367-378
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• 2006

A mobile phone has became as a payment tool in e-commerce and on-line banking areas. This trend of a payment system using various types of mobile devices is rapidly growing, especially in the Internet transaction and small-money payment. Hence, there will be a need to define its standard for secure and safe payment technology. In this thesis, we consider the service types of the current mobile payments and the authentication method, investigate the disadvantages, problems and their solutions for smart and secure payment. Also, we propose a novel authentication method which is easily adopted without modification and addition of the existed mobile hardware platform. Also, we present a simple implementation as a demonstration version. Based on virtual machine (VM) approach, the proposed model is to use a pseudo-random number which is confirmed by the VM in a user's mobile phone and then is sent to the authentication site. This is more secure and safe rather than use of a random number received by the previous SMS. For this payment operation, a user should register the serial number at the first step after downloading the VM software, by which can prevent the illegal payment use by a mobile copy-phone. Compared with the previous SMS approach, the proposed method can reduce the amount of packet size to 30% as well as the time. Therefore, the VM-based method is superior to the previous approaches in the viewpoint of security, packet size and transaction time.