• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.4 s.304
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• pp.59-68
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• 2005

In this paper, we design a PCI Express controller for future communication system The controller supports the full functionality of Transaction Layer and Data Link Layer of PCI Express. The designed controller has the proposed transmitter buffer architecture to obey Replay mechanism. This scheme merges the transmitting buffer and the replay buffer. The proposed buffer has the higher data transfer efficiency than the conventional buffer architecture because it can dynamically adjust size of a replay buffer space. We also design transmitter of Transmitter Transaction Layer to effectively support the proposed buffer, The receiver device of PCI Express must possess the buffer for three types of transaction to support Flow Control. And it must report the amount of the buffer space regularly to the Port at the opposite end of the link. We propose the simple receiver buffer scheme using only one buffer to easily support Flow Control. And the designed controller is verified under proposed test bench

• Journal of KIISE:Databases
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• v.30 no.6
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• pp.629-640
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• 2003

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. In the SD cluster, a transaction routing corresponds to select a node for an incoming transaction to be executed. An affinity-based routing can increase local buffer hit ratio of each node by clustering transactions referencing similar data to be executed on the same node. However, the affinity-based routing is very much non-adaptive to the changes in the system load, and thus a specific node will be overloaded if transactions in some class are congested. In this paper, we propose a dynamic transaction routing scheme that can achieve an optimal balance between affinity-based routing and dynamic load balancing of all the nodes in the SD cluster. The proposed scheme is novel in the sense that it can improve the system performance by increasing the local buffer hit ratio and reducing the buffer invalidation overhead.

• The Journal of Information Systems
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• v.6 no.1
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• pp.159-180
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• 1997

Database sharing system(DBSS) refers to a system for high performance transaction processing. In DBSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory, a separate copy of operating system, and a DBMS. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. However, since multiple nodes may be simultaneously cached a page, cache consistency must be ensured so that every node can always access the latest version of pages. In this paper, we propose efficient buffer invalidation schemes in DBSS, where the database is logically partitioned using primary copy authority to reduce locking overhead. The proposed schemes can improve performance by reducing the disk access overhead and the message overhead due to maintaining cache consistency. Furthermore, they can show good performance when database workloads are varied dynamically.

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.469-480
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• 2008

A shared disk (SD) cluster couples multiple nodes for high performance transaction processing, and all the coupled nodes share a common database at the disk level. To reduce the number of disk accesses, each node caches database pages in its memory buffer. Since a particular page may be cached simultaneously in different nodes, cache consistency should be maintained to ensure that nodes can always access the most recent version of database pages. Most cache consistency schemes proposed in the SD cluster adopted LRU as a buffer replacement algorithm. In this paper, we first present four buffer replacement algorithms that consider the characteristics of the SD cluster. Then we compare the performance of the buffer replacement algorithms. We perform the experiments on a variety of cluster configurations and database workloads. The experiment results show that the proposed algorithms achieve performance improvement up to 5 times of LRU algorithm.

• Journal of Korea Multimedia Society
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• v.12 no.1
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• pp.41-49
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• 2009

Smart Card is currently more popular in mobile communication, and smart card with java card platform becomes a standard choice. Java card has a problem that it gets lost working data when power is off. Transaction is the idea to solve a problem of data loss, but it accepts only one transaction process, and other transaction process need to hold until the current working transaction is finished. This might be a factor to drop the Java card's performance. In this paper, we define a rule of dual-lock which can run transaction at multiple transaction buffer as a method for a better java card performance, and we suggest this rule to improve a capability of transaction process. From this research, we are able to improve the data stability, reduce the java card transaction delay time, and get a higher processing speed of java card.

• Journal of the Korean Data and Information Science Society
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• v.20 no.1
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• pp.125-137
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• 2009

Smart card has a small sized micro computer chip. This chip contains processor, RAM, ROM, clock, bus system and crypto-co-processor. Hence it is more expensive, complicated and secure chip compared with RFID tag. The main application area of smart card is e-banking and secure communications. There are two kinds of smart card platforms; open platform and closed one. Java card is the most popular open platform because of its security, platform independency, fast developing cycle. However, the speed of Java card is slower than other ones, hence there have been hot research topics to improve the performance of Java card. In this paper, we propose an efficient transaction buffer management to improve the performance of Java card. The experimental result shows the advantage of our method.

• Journal of KIISE:Databases
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• v.36 no.5
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• pp.399-404
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• 2009

In a multiple-server DBMS using the share-disk model, when a server process updates data, the updated ones are not immediately reflected to the buffers of the other server processes. Thus, the other server processes may read invalid data. In this paper, we propose a novel method to solve this problem. In this method the server process stores the identifiers and timestamps of the pages that have been updated during a transaction into the coherency volume when the transaction commits. Then, the server process invalidates its buffers of the pages updated by the other server processes by accessing the coherency volume when the lock is acquired, and, subsequently, read the up-to-date versions of the pages from disk. This method needs only a very small coherency volume and shows a good performance because the amount of data that need to be accessed is very small.

• The KIPS Transactions:PartD
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• v.10D no.7
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• pp.1067-1076
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• 2003

Database sharing system (DSS) refers to a system for high performance transaction processing. In DSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory and a separate copy of operating system. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. In this paper, we propose a dynamic transaction routing algorithm to balance the load of each node in the DSS. The proposed algorithm is novel in the sense that it can support node-specific locality of reference by utilizing the primary copy authority assigned to each node; hence, it can achieve better cache hit ratios and thus fewer disk I/Os. Furthermore, the proposed algorithm avoids a specific node being overloaded by considering the current workload of each node. To evaluate the performance of the proposed algorithm, we develop a simulation model of the DSS, and then analyze the simulation results. The results show that the proposed algorithm outperforms the existing algorithms in the transaction processing rate. Especially the proposed algorithm shows better performance when the number of concurrently executed transactions is high and the data page access patterns of the transactions are not equally distributed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.57-64
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• 2008

In this paper, we propose a system-level simulator for the performance analysis of a Solid-State Disk (SSD) in PC environment by using TLM (Transaction Level Modeling) method. Our method provides quantitative analysis for a variety of architectural choices of PC system as well as SSD. Also, it drastically reduces the analysis time compared to the conventional RTL (Register Transfer Level) modeling method. To show the effectiveness of the proposed simulator, we performed several explorations of PC architecture as well as SSD. More specifically, we measured the performance impact of the hit rate of a cache buffer which temporarily stores the data from PC. Also, we analyzed the performance variation of SSD for various NAND Flash memories which show different response time with our simulator. These experimental results show that our simulator can be effectively utilized for the architecture exploration of SSD as well as PC.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.1-5
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• 2011

We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.