• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.1
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• pp.93.2-93.2
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• 2012

Point Spread Function (PSF) is one of the most important optical characteristics for describing the performance of a telescope. And a concept of subpixelization is inevitable in evaluating the undersampled PSF (Shin and Sakurai 2009). Then, the internal structure of Yohkoh SXT CCD pixel is not uniform: For the top half of pixel area, the X-ray should pass a so-called gate structure where the charges are transferred to an output amplifier. This gate structure shows energy-dependent sensitivity (Tsuneta et al. 1991). For example, for Al-K (8.34 A) X-ray emission, the transmission of the polysilicon gate is about 0.9. Also, for the peak coronal response of the SXT thin filters, around 17 angstrom (0.729 keV), the transmission of the gate is about 0.6, falling off sharply towards longer wavelengths. It should be noted that this spectrally dependent non-uniform response of each CCD pixel will certainly have a noticeable effect on the properties of the PSF at longer wavelengths. Therefore, especially for analyzing the undersampled PSF of low energy source, a careful consideration of non-uniform internal pixel structure is required in determining the shape of the PSF core. The details on the effect of gate structure will be introduced in our presentation.

• Journal of Information Display
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• v.7 no.1
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• pp.1-6
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• 2006

A 10" carbon nanotube field emission display device was fabricated with a novel structure with a hopping electron spacer (HES) by screen printing technique. HES plays a role of preventing the broadening of electron beams emitted from carbon nanotubes without electrical discharge during operation. The structure of the novel tetrode is composed of carbon nanotube emitters on a cathode electrode, a gate electrode, an extracting electrode coated on the top side of a HES, and an anode. HES contains funnel-shaped holes of which the inner surfaces are coated with MgO. Electrons extracted through the gate are collected inside the funnel-shaped holes. They hop along the hole surface to the top extracting electrode. In this study the effects of the addition of HES on emission characteristics of field emission display were investigated. An active ozone treatment for the complete removal of residues of organic binders in the emitter devices was applied to the field emission display panel as a post-treatment.

• Journal of the Korean Applied Science and Technology
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• v.25 no.3
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• pp.388-394
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• 2008

본 논문에서는 용액 공정을 이용한 고분자 절연층을 갖는 top-gate 구조의 펜타센 박막 트랜지스터(Thin Film Transistor, TFT)의 특성을 연구하였다. Top-gate 구조의 펜타센 TFT 제작에 앞서 유기 반도체인 펜타센의 결정성 성장을 돕기 위해서 가교된 PVP (cross-linked poly(4-vinylphenol))를 유리 기판 상에 스핀 코팅을 이용하여 형성한 후, 노광 공정을 통해 니켈/은 구조를 갖는 채널 길이 $10{\mu}m$의 소오스, 드레인 전극을 형성하였다. 그리고 열 증착을 이용하여 60 nm 두께의 펜타센 층을 성막하였고, 고분자 절연체로서 PVA(polyvinyl alchol) 또는 가교된 PVA를 용액공정인 스핀 코팅을 이용하여 형성한 후 열 증착으로 알루미늄 게이트 전극을 성막하였다. 이로써 제작된 소자들의 전기적 특성을 확인한 결과 가교된 PVA를 사용한 펜타센 TFT 보다 PVA를 게이트 절연체로 사용한 소자가 전기적 특성이 우수한 것으로 관찰되었다. 이는 PVA의 가교 공정에 의한 펜타센 박막의 성능 퇴화에 기인한 것으로 사료된다. 실험 결과 $0.9{\mu}m$ 두께의 PVA 게이트 절연막을 사용한 top-gate 구조의 펜타센 TFT의 전계 효과 이동도와 문턱전압, 그리고 전류 점멸비는 각각, 약 $3.9{\times}10^{-3}\;cm^2/Vs$, -11.5 V, $3{\times}10^5$으로써 본 연구에서 제안된 소자가 용액 공정형 top-gate 유기 TFT 소자로서 우수한 성능을 나타냄을 알 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.401-406
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• 2015

The change of subthreshold swing for channel length of asymmetric double gate(DG) MOSFET has been analyzed. The subthreshold swing is the important factor to determine digital chracteristics of transistor and is degraded with reduction of channel. The subthreshold swing for channel length of the DGMOSFET developed to solve this problem is investigated for channel thickness, oxide thickness, top and bottom gate voltage and doping concentration. Especially the subthreshold swing for asymmetric DGMOSFET to be able to be fabricated with different top and bottom gate structure is investigated in detail for bottom gate voltage and bottom oxide thickness. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. As a result, subthreshold swing is sensitively changed according to top and bottom gate voltage, channel doping concentration and channel dimension.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1008-1011
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• 2005

In this study, the field emission display with carbon nanotube emitter is developed for the large size HDTV application. Two structures for electron beam focusing are developed on the typical top-gate cathode. The metal grid and focusing gate structure are proved to be effective for the focusing. The data switching voltage for the double gate structure is lower than 30V which is competitive value in respect of the cost for driver electronics. The brightness and color gamut are comparable to those of the commercial product such as CRT.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1466-1469
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• 2008

We have fabricated 2.5 inch QQCIF AM-OLED panel driven by ZnO-TFT on a plastic substrate for the first time. The number of photo mask for the whole panel process was 5 and the TFT structure was top gate with active protection layer as a first gate insulator. Optimizing the process for the substrate buffer layer, active layer, ZnO protection layer, and gate insulator was key factor to achieve the TFT performance enough to drive OLED. The ZnO TFT has mobility of $5.4\;cm^2/V.s$, turn on voltage of -6.8 V, sub-threshold swing of 0.39 V/decade, and on/off ratio of $1.7{\times}10^9$. Although whole process temperature is below $150^{\circ}C$ to be suitable for the plastic substrate, performance of ZnO TFT was comparable to that fabricated at higher temperature on the glass.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• ETRI Journal
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• v.27 no.3
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.