• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.287.2-287.2
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• 2016

Silicon has considerably good characteristics on electron, hole mobility and its price. With 2-D sinlge-layer Graphene/n-Si heterojunction solar cell shows that in one sun condition exhibit power conversion efficiency(PCE) of 10.1%. This photovoltaic effect was achieved by applying gate voltage to the Schottky junction of the heterostructure solar cell. Energy band diagram shows that Schottky barrier between Si and graphene can be adjust by the external electric field. because of the fermi level of the graphene can be changed by external gate voltage, we can control the Schottkky barrier of the heterostructure solar cell. The ratio between generated power of solar cell and consumption electrical power is remarkable. Since we use the graphene as the top gate electrode, most of the sun light can penetrate into the active area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1422-1428
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.223-226
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• 2003

We propose an improvement method for a $\underline{G}ate$ $\underline{OX}ide(GOX)$ thinning at the edge of $\underline{S}hallow$ $\underline{T}rench$ $\underline{I}solation(STI)$, when STI is adopted to Dual Gate Oxide(DGOX) Process. In the case of SOC(System On-a-Chip), the DGOX process is usually used for realizing both a low and a high voltage parts in one chip. However, it is found that the severe GOX thinning occurs from at STI top edge region and a dent profile exists at the top edge of STI, when conventional DGOX and STI process carried out in high density device chip. In order to overcome this problem, a new DGOX process is tried in this study. And we are able to prevent the GOX thinning by H2 anneal, partially SiN liner skip, and a method which is merged a thick sidewall oxide(S/O) with a SiN pull-back process. Therefore, a good subthreshold characteristics without a double hump is obtained by the prevention of a GOX thinning and a deep dent profile.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.741-744
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.212-217
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• 2002

A new technique for highly controllable trench corner rounding at the top and bottom of the trench using pull-back and hydrogen annealing has been developed and investigated. The pull-back process could control the trench corner rounding radius at the top comers of the trench. The silicon migration generated by hydrogen annealing at the trench coiners provided (111) and (311) crystal planes and gave a uniform gate-oxide thickness, resulting in high reliable trench DMOSFETs with highly breakdown voltages and low leakage currents. The breakdown voltage of a trench DMOSFET fabricated using hydrogen annealing was increased by 25% compared with a conventional DMOSFET. The reasonable drain current of 45.3 A was obtained when a gate voltage of 10 V was supplied. The on-resistance of the trench gate DMOSFET fabricated using the trench cell of 45,000 was about 55 m(at a gate voltage of 10 V under a drain current of 5 A.

• Korean Journal of Cognitive Science
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• v.10 no.3
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• pp.1.2-1.2
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• 1999

시각적 선택에 대한 과거 정신물리학적, 신경 생리학적 연구결과를 토대로 Feature Gate 라는 신경 망 모형을 제안하였다. 이 모형에는 공간 배치도가 위계 적으로 구성되어 있으며, 정보의 흐름이 위계의 각 수준으로부터 그 다음 수준으로 넘어갈 때 주의 게이트에 의해 조절되도록 되어 있다. 주의 게이트들은 독특한 세부 특징을 가진 위치에 반응하는 상향식 시스템과 표적 세부 특징이 있는 위치에 반응하는 하향식 기제 모두에 의해 조절된다. 본 연구는 Feature Gate 모형의 하향식 기제에 초점을 맞추어 모형을 설명하고, 현재 다른 모형들이 설명하지 못하는 Moran & Desimone(1985)의 연구결과를 이 모형이 어떻게 설명하는지를 제시하고자 한다. Feature Gate 모형은 병렬 적인 세부특징 검색, 계열 적 접합표적 검색, 단서에 의한 주의의 점진적 감소 모형, 세부특징-주도적인 공간적 선택, 주의의 분할, 방해자극 위치의 억제, 주변 억제 등을 포함한 시각적 주의 연구의 여러 가지 많은 현상들을 설명하는데 하나의 일관적인 해석을 제공해 준다. 앞으로 이 모형을 더욱 확장, 발전 시켜 세부특징의 조합된 배열에 반응하는 상위 수준의 유닛을 사용한다면 시각적 선택과정이 포함된 형태 재인 모형으로 개발될 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.11
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.87-93
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• 2020

This study proposes a gate driver that operates semiconductor switches in the bipolar pulsed power modulator. The proposed gate driver was designed to receive isolated power and synchronized signals through the gate transformer. The gate circuit has a separate delay in the on-and-off operation to prevent a short circuit between the top and bottom switches of each leg. On the basis of the proposed gate circuit, a bipolar pulsed power modulator prototype with a 2.5 kV/100 A rating was developed. Finally, the bipolar pulsed power modulator was tested under resistive load and plasma reactor load conditions. It is verified that the proposed gate driver can be applied to a bipolar pulsed power modulator.