• 대한산업공학회지
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• 제31권1호
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• pp.36-43
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• 2005

It is the basic requirement of design process of parts assembly to specify geometric dimensions and tolerances of product characteristics. Among them, tolerance stack analysis is one of the important methods to specify tolerance zone. Tolerance stack analysis is to calculate gap using tolerances which includes geometric and coordinate dimensions. In this study, we suggested more general method called the virtual method to analyze tolerance stack. In virtual method, tolerance zone is formed by combination of dimensional tolerance, geometric tolerance and bonus tolerance. Also tolerance zone is classified by virtual boundary condition and resultant boundary condition. So gap can be defined by combination of virtual boundary and/or resultant boundary. Several examples are used to show the effectiveness of new method comparing to other methods.

• 대한안전경영과학회:학술대회논문집
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• 대한안전경영과학회 2002년도 춘계학술대회
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• pp.99-103
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• 2002

It is the basic requirement of product characteristics to specify geometric dimensions and tolerances during design process of parts assembly. Therefore, there are many tolerance stack analysis method to explain tolerance zone. Tolerance stack analysis is to calculate gap using tolerances which includes geometric and coordinate dimension. In this study, we compared several different stack analysis method and try to suggest more general method called the Virtual Method to analyze tolerance stack.

• 품질경영학회지
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• 제22권4호
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• pp.79-101
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• 1994

In modern manufacturing, a product consists of many components created by different processes. Variations in the individual component dimensions and in the processes may result in unacceptable final assemblies. Thus, engineers have increased pressure to properly set tolerance specifications for individual components and to control manufacturing processes. When a proper variation stack-up analysis is not performed for all of the components in a functional system, all component parts can be within specifications, but the final assembly may not be functional. Thus, in order to improve the performance of the final assembly, a proper variation stack-up analysis is essential for specifying dimensional tolerances and process control. This research provides a detailed case example of the use of variation stack-up analysis using a Monte Carlo simulation method to improve the defect rate of a complex process, which is the commutator brush track undercut process of an armature assembly of a small motor. Variations in individual component dimensions and process mean shifts cause high defect rate, Since some dimensional characteristics have non-normal distributions and the stack-up function is non-linear, the Monte Carlo simulation method is used.

• 대한임베디드공학회논문지
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• 제11권5호
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• pp.259-265
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• 2016

In this paper, we present an architecture for the fault isolation by applying virtualization-based multi-stack technologies. We propose the simultaneous sharing and switching mechanism using virtualied serial communications. Each guest OS has its own virtual serial device. The distribution module provides communications between the guest OS's through the virtual serial devices and simultaneously detect the liveness of the guest OS. The suggested mechanism has been implemented in VirtualBox and shows satisfactory performance in transmission speed and data sharing capability with virtual RS232.

• 한국CDE학회논문집
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• 제17권6호
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• pp.398-408
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• 2012

This paper investigates the tolerance stack-up in a commercial sliding-type mobile phone model developed by a Korean electronics company, with focus on the dimensional quality of the gap between the sliding top and the main body. The tolerance analysis in this study is done using a commercial software package, which runs Monte Carlo simulations to produce the statistical distributions of the gap size at desired locations. Such an analysis revealed that the original design did not yield the desired dimensional quality of the gap. Through a series of systematic analyses and syntheses, an improved design is proposed for the nominal dimensions and tolerances of selected features of the parts. The proposed design was validated, through tolerance analysis simulation, to meet the desired requirement of the gap quality.

• 전기전자학회논문지
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• 제23권1호
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• pp.338-341
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• 2019

본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 특성을 향상시킨 새로운 구조의 ESD소자를 제안하고 특정 application의 각 요구전압에 최적화된 설계를 위한 N-stack 기술에 대하여 검증한다. 주요 파라미터인 홀딩전압과 트리거전압에 대하여 특성을 파악하고 감내특성의 지표인 온도특성 또한 검증한다. well영역의 추가구성과 기생 npn BJT를 추가로 직렬 연결된 구조를 형성하여 보다 향상된 전기적 특성을 갖는다. 특성 검증을 위해 synopsys 사의 T-cad simulation tool을 이용하였다.

• 전기전자학회논문지
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• 제21권3호
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• pp.234-239
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• 2017

본 논문에서는 PMOS 구조를 삽입한 새로운 구조의 SCR(Silicon Controlled Rectifier)기반 ESD(Electrostatic Discharge) 보호소자를 제안한다. 제안된 ESD 보호회로는 내부에 PMOS가 추가적으로 형성된 구조적 특징을 지니며, Latch-up 면역 특성과 향상된 감내특성을 갖는다. TCAD 시뮬레이션을 이용하여 기존의 ESD 보호회로와 특성을 비교 분석하였다. 시뮬레이션 분석 결과, 제안된 보호 ESD 보호회로는 기존 SCR 기반 ESD 보호소자 HHVSCR(High Holding Voltage SCR)과 같은 우수한 Latch-up 면역 특성을 지닌다. 또한 HBM(Human Body Model) 최대온도 테스트 결과에 따르면, 제안된 ESD 보호회로는 355K의 최대온도 수치를 가지며, 이는 기존 HHVSCR의 373K와 비교하여 대략 20K가량 낮은 온도특성으로, 더욱 향상된 감내특성을 갖는 것으로 확인되었다. 제안된 ESD 보호소자는 N-STACK 기술을 적용하여 설계하여 전압별 적용이 가능함을 시뮬레이션을 통하여 검증하였다. 시뮬레이터로 시뮬레이션을 해본 결과, 제안된 ESD 보호회로는 단일 구조에서 2.5V의 홀딩전압 특성을 지니며, N배수의 증배에 따라 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V로 증가된 홀딩전압을 갖는 것을 확인하였다.

• 한국수소및신에너지학회논문집
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• 제18권4호
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• pp.439-445
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• 2007

Proton exchange membrane Fuel Cells(PEMFCs) have been spotlighted because of their broad potential application for potable electrical devices, automobiles and residential usages. However, their utilization is limited to low temperature operation due to the electrolyte dehydration at high temperature. High temperature PEMFC operation offers high CO tolerance and easy water management. This review presents development of high temperature($120{\sim}200^{\circ}C$) PEMFC. Especially, PEMFC which is based on acid-doped PBI membrane is discussed.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2002년도 춘계학술발표논문집 (상)
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• pp.381-384
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• 2002

This paper describes the motivation, design and performance of bi-active Load balancer in Linux Virtual Server. The goal of bi-active Load balancer is to provide a framework to build highly scalable, fault-tolerant services using a large cluster of commodity servers. The TCP/IP stack of Linux Kernel is extended to support three IP load balancing techniques, which can make parallel services of different kinds of server clusters to appear as a service on a single IP address. Scalability is achieved by transparently adding or removing a node in the cluster. and high availability is provided by detecting node or daemon failures and reconfiguring the system appropriately. Extensive simulation reveals that the proposed approach improves the reply rate about 20% compared to earlier design.

• Journal of Information Processing Systems
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• 제18권6호
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• pp.741-754
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• 2022

Openstack is widely used as a representative open-source infrastructure of the service (IaaS) platform. The Openstack Identity Service is a centralized approach component based on the token including the Memcached for cache, which is the in-memory key-value store. Token validation requests are concentrated on the centralized server as the number of differently encrypted tokens increases. This paper proposes the practical Byzantine fault tolerance (PBFT) blockchain-based Openstack Identity Service, which can improve the performance efficiency and reduce security vulnerabilities through a PBFT blockchain framework-based decentralized approach. The experiment conducted by using the Apache JMeter demonstrated that latency was improved by more than 33.99% and 72.57% in the PBFT blockchain-based Openstack Identity Service, compared to the Openstack Identity Service, for 500 and 1,000 differently encrypted tokens, respectively.