• 한국정보통신학회논문지
• /
• 제8권4호
• /
• pp.767-773
• /
• 2004

UWB(Ultra-Wide Bandwidth) 통신 시스템은 멀티미디어 정보와 같은 대량, 고속 통신을 요구하는 추세에 부합하는 통신 방식으로 맡은 관심을 받고 있다. UWB 통신 방식에서 중요한 특징은 시간 영역에서 매우 폭이 좁은 펄스를 사용하여 정보를 전송하며, 펄스의 위치를 변조시키는 PPM(Pulse Position Modulation)을 사용하는 점이다. 따라서, 송신기와 수신기의 타이밍 지터(timing jitter)는 매우 중요한 역할을 하며, 이들 지터가 UWB 통신 시스템에 미치는 영향을 정확히 해석하는 것은 매우 중요하다. 따라서 본 논문에서는 이와 같은 지터의 영향을 해석하는 방법을 제시하였다. 이때 본 논문에서 계산한 것은 M-진 PPM UWB 통신 시스템 용량(capacity)이다. 또한, 다중 사용자 환경에서 지터의 영향도 함께 해석하였다.

• Journal of Positioning, Navigation, and Timing
• /
• 제12권3호
• /
• pp.245-255
• /
• 2023

Time comparison techniques are necessary for generating and keeping Coordinated Universal Time (UTC) and distributing standard time clocks. Global Navigation Satellite System (GNSS) Common View, GNSS All-in-View, Two-Way Satellite Time and Frequency Transfer (TWSTFT), Very Long Baseline Interferometry (VLBI), optical fiber, and Network Time Protocol (NTP) based methods have been used for time comparison. In these methods, GNSS based time comparison techniques are widely used for time synchronization in critical national infrastructures and in common areas of application such as finance, military, and wireless communication. However, GNSS-based time comparison techniques are vulnerable to jamming or interference environments and it is difficult to respond to GNSS signal disconnection according to the international situation. In response, in this paper, Code-Division Multiple Access (CDMA) based All-to-All TWSTFT operation method is proposed. A software-based simulation platform also was designed for performance analysis in multi-TWSTFT signal environments. Furthermore, code and carrier measurement jitters were calculated in multi-signal environments using the designed simulation platform. By using the technique proposed in this paper, it is anticipated that the TWSTFT-based time comparison method will be used in various fields and satisfy high-performance requirements such as those of a GNSS master station and power plant network reference station.

• 대한전자공학회논문지SD
• /
• 제42권9호
• /
• pp.35-40
• /
• 2005

본 논문에서는 1.6Gb/s에서 동작하는 digitally controlled phase-locked loop (DCPLL)를 제안한다. DCPLL은 일반적인 아날로그 PLL과 tracking analog-to-digital 변환기를 결합한 구조이다. 제안한 DCPLL에서는 tracking ADC의 출력이 voltage controlled oscillator (VCO)의 제어 전압을 생성한다. 일반적으로 사용되는 digital PLL (DPLL)은 digitally controlled oscillator (DCO)와 time-to-digit converter (TDC)로 구성된다 DCO와 TDC를 사용한 DPLL은 시간 스텝이 작을 수 록 jitter 특성이 향상되지만 전력소모는 커진다. 이 논문에서 제안한 DCPLL은 DPLL의 핵심요소인 DCO와 TDC를 사용하지 않았기 때문에 jitter, 면적, 전력소모 측면에서 유리하다. DCPLL은 $0.18\mu$m 4-metal CMOS공정을 이용하여 제작하였고 면적은 1mm $\times$0.35mm를 차지한다. 1.8V 단일 전원전압으로 정상동작에서는 59mW, power-down 모드에서는 $984\mu$W 전력을 소모하고 16.8ps rms jitter를 갖는다.

• 제어로봇시스템학회논문지
• /
• 제15권11호
• /
• pp.1144-1149
• /
• 2009

This paper deals with the time synchronization problem over SpaceWire links. SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper, faster on-board data handling in spacecraft. The standard defines Time-Code for time distribution over SpaceWire network. When a Time-Code is transmitted, transmission delay and jitter is unavoidable. In this paper, a mechanism to remove Time-Code transmission delay and jitter over SpaceWire links is proposed and implemented with FPGA for validation. The proposed mechanism achieves high resolution clock synchronization over SpaceWire links, complies with the standard and can be easily adopted over SpaceWire network.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
• /
• pp.2806-2808
• /
• 2005

The Controller Area Network (CAN) is being widely used for real-time control application and small-scale distributed computer controller systems. When the stuff bits are generated by bit-stuffing mechanism in the CAN network, it causes jitter including variations in response time and delay. In order to eliminate this jitter, stuff bit must be controlled to minimize the response time and reduce the variation of data transmission time. At first, this paper shows that conventional CAN protocol causes the transmission time delay. Secondly, this paper proposes the method to reduce the stuff bits by restriction of available identifier. Finally, data manipulation method can be reduced the number of stuff-bits in the data field. The proposed restriction method of ID and manipulating data field are pretty useful to the real-time control strategy with respect to performance. These procedures are implemented in local controllers of the ISHURO (Inha Semyung Humanoid Robot).

• 대한임베디드공학회논문지
• /
• 제12권4호
• /
• pp.239-246
• /
• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• 전자공학회논문지
• /
• 제50권10호
• /
• pp.76-81
• /
• 2013

130nm CMOS 공정 라이브러리를 이용하여 125MHz로 동작하는 새로운 위상 주파수 검출기 기반 DPLL을 설계하였다. 이 DPLL은 중간 주파수대 응용을 위해 지터와 록 시간을 줄이려고 전형적인 DPLL에 반전 에지 검출기를 포함하고 있다. XOR 기반 반전 에지 검출기들은 출력을 보다 빨리 변화시키기 위하여 기준 신호보다 빠른 전이를 얻는데 사용된다. HSPICE 시뮬 레이터는 모의실험을 위해 Cadence환경에서 사용되었다. 제안된 위상 주파수 검출기를 가진 DPLL의 성능은 종래의 위상 주 파수 검출기를 가진 것의 성능과 비교하였다. 종래의 PLL은 약 0.1245 ns의 최대 지터를 가지고 록 하는데 최소 $2.144{\mu}s$가 걸린 반면에, 제안한 검출기를 가진 PLL은 약 0.1142 ns의 최대 지터를 가지고 록 하는데 $0.304{\mu}s$가 걸린다.

• Journal of electromagnetic engineering and science
• /
• 제18권3호
• /
• pp.169-174
• /
• 2018

In this paper, we propose an estimation method using multiple in-phase and quadrature (IQ) signals of different frequencies to evaluate the sample-time errors in the sampling oscilloscope. The estimator is implemented by ODRPACK, and a novel iteration scheme is applied to achieve fast convergence without any prior information. Monte-Carlo simulation is conducted to confirm the proposed method. It clearly shows that the multiple IQ approach achieves more accurate results compared to the conventional method. Finally, the criteria for the frequency selection and the signal capture time are investigated.

• ETRI Journal
• /
• 제29권6호
• /
• pp.716-724
• /
• 2007

As ultra-wideband impulse radio (UWB-IR) uses short-duration impulse signals of nanoseconds, even a small number of timing errors can cause a detrimental effect on system performance. A delay-locked loop (DLL) is proposed to synchronize and reduce timing errors. The design of the DLL is vital for UWB systems. In this paper, an improved DLL is introduced to a UWB-IR time-hopping spread-spectrum system. Instead of using only two central correlator branches as in a conventional DLL, the proposed system uses two additional correlator branches with different delay parameters and different weight parameters. The performance of the proposed schemes with the optimal parameters is compared with that of traditional schemes through simulation: the proposed four-branch DLLs achieves less tracking jitter or a longer mean time to lose lock (MTLL) than the conventional two-branch DLLs if proper parameters are chosen.