• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• 한국통신학회논문지
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• 제26권6A호
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• pp.1067-1077
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• 2001

본 논문에서는 결함의 영향을 받지 않고 동작할 수 있는 AVTMR(All Voting Triple Modular Redundancy) 시스템과 듀얼 듀플렉스(Dual-duplex) 시스템을 설계하고, 각 시스템의 평가를 통하여 RAMS(Reliability, Avaliability, Maintainability, Safety)를 비교하였다. ABTMR 시스템은 3중화된 보터(voter)를 사용하여 설계를 하였으며, 듀얼 듀플렉스 시스템은 비교기(comparator)를 이용하여 시스템을 설계하였다. 각 시스템은 버스 레벨로 데이터를 비교하도록 설계하였으며, 시스템 평가를 위해서 소자의 고장율은 MILSPEC-217F에 기반을 두고 RELEX6.0을 이용하였고, 마코브 모델(Markov model)을 이용하여 시스템의 RAMS를 평가하였다. 본 논문에서는 각 시스템을 MC68000을 기반으로 설계하여, 각각 시스템에 사용되는 비용 및 시스템이 어느 부분에서 선호될 수 있는가를 RAMS 및 MTTF(Mean Time To Failure)를 통하여 선택할 수 있는 기반을 제시하도록 나타내고 있다. 이러한 AVTMR이나 듀얼 듀플렉스 시스템(dual-duplex system)은 결함 허용 시스템(fault tolerant system)으로 인간의 생명과 직접적인 관련이 있는 고속철도 시스템이나 항공기 시스템에 적용될 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2552-2554
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• 2001

This paper presents a front-end electronic circuits for signal detection on multi-gap resistive plate. The input to the circuit is the signal(voltage : -800mv, frequency : 20${\sim}$40MHZ, noise : 50mv, 1GHz) from the multi-gap resistive plate chamber and the output is the 5v pulse signal. The front-end electronic circuit consists of preamplifier, peak-detector, and comparator. Spice simulation show that the circuit has the better response time than the one of the conventional measuring instruments.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권4호
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• pp.168-176
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• 2001

In this paper, we develop a dual-duplex system which detects a fault by hardware comparator and switches to hot standby redundancy. This system is designed on the basis of MC68000 and can be used in VMEbus. To improve reliability, the dual-duplex system is designed in dual modular redundancy. The failure rate of electrical element is calculated in MILSPEC-217F, and the system RAMS(Reliability, Availiability, Maintainability and Safety) and MTTF(Mean Time to Failure) are evaluated by Markov modeling method. As the evaluation result shows improved reliability, it can be used as a component hardware for a highly reliable control system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 B
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• pp.1208-1210
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• 2003

Most of all, DTC drive is very simple in its implementation because it needs only two hysteresis comparator and switching vector table for both flux and torque control. The amplitude of hysteresis band greatly influences on the drive performance such as flux and torque ripple and inverter switching frequency. In this paper the influence of the amplitudes of flux and torque hysteresis bands and sampling time of control program on the torque and flux ripples are investigated. Simulation results confirm the superiority of the DTC under the proposed method over the conventional DTC.

• 조명전기설비학회논문지
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• 제29권8호
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• pp.40-48
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• 2015

In this paper, battery charging and discharging circuit with a single voltage power supply is proposed. The proposed circuit has the separated current path and charging-monitoring sequence control scheme. In the charging sequence, the proposed 2-level comparator combined with control signal of the micro-processor can control the constant charging current to protect the over current of the battery. Furthermore, the proposed circuit uses a periodic main power switch control to detect the discharging characteristics to estimate the approximated battery life-time. In the experiments, the proposed emergency power supply for emergency call system has 89% efficiency with 98% power factor. And the proposed sequence control scheme is well operated in the designed emergency power system.

• 한국컴퓨터정보학회논문지
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• 제24권2호
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• pp.57-66
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• 2019

This paper compared the performance with an overview of channel equalization techniques used in high-speed serial transceivers, including the homogeneous architecture and associated components for the GHz interconnect of backplane and cable channels. It also used the MATLAB tool to present system analysis and simulation results for continuous time equivalent structures. In the case of conventional continuous equalization, high frequency deficits occur due to the use of a comparator that is difficult to implement as well as the low speed limit. In this paper, the channel equalization technique based on the power spectrum analysis of clocks was used to compensate for the frequency loss, and the application of the TX+Channel and TX+Equalizer filters enabled the measurement of attenuation and equivalence without comparators. The application of blender and band-pass filters at high speeds also showed significant effectiveness.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 조명전기설비학회논문지
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• 제26권6호
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.