Browse > Article
http://dx.doi.org/10.9708/jksci.2019.24.02.057

Channel Equalization for High-speed applications using MATLAB  

Kim, Young-Min (Dept. of Mechatronics, Korea Polytechnics University)
Park, Tae-Jin (Dept. of College of General Education, Silla University)
Abstract
This paper compared the performance with an overview of channel equalization techniques used in high-speed serial transceivers, including the homogeneous architecture and associated components for the GHz interconnect of backplane and cable channels. It also used the MATLAB tool to present system analysis and simulation results for continuous time equivalent structures. In the case of conventional continuous equalization, high frequency deficits occur due to the use of a comparator that is difficult to implement as well as the low speed limit. In this paper, the channel equalization technique based on the power spectrum analysis of clocks was used to compensate for the frequency loss, and the application of the TX+Channel and TX+Equalizer filters enabled the measurement of attenuation and equivalence without comparators. The application of blender and band-pass filters at high speeds also showed significant effectiveness.
Keywords
Channel equalization techniques; Workload; GHZ interconnect; MATLAB simulation;
Citations & Related Records
연도 인용수 순위
  • Reference
1 R. Payne et al., "A 6.25-Gb/s binary transceiver in 0.13-_m CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Circuits, vol. 40, no. 12, pp. 2646-2657, Dec.2005.   DOI
2 T. Beukema et al., "A 6.4-Gb/s CMOS serDes core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.   DOI
3 K. Krishna, D. A. Yokoyama-Martin, S. Wolfer, C. Jones, M. Loikkanen, J. Parker, R. Segelken, J. L. Sonntag, J. Stonick, S. Titus, and D. Weinlader, "A multigigabit backplane transceiver core in 0.13 _m CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Solid-State Circuits, pp. 2658-2666, Dec. 2005.
4 Ravi Kollipara et.al. "Impact of Manufacturing Variations on Backplane System Performance" DesignCon 2005, SantaClara,CA
5 Jared Zerbe et. al. "Comparison of adaptive and non-adaptive equalization methods in high-performance backplanes" DesignCon 2005, SantaClara,CA
6 A. Shoval, O. Shoaei, K. Lee, and R. Leonwich, CMOS mixed-signal 100 Mb/s receive architecture for fast ethernet," in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp. 253-256.
7 M. Altmann, J. M. Caia, R. Morle, M. Dunsmore, Y. Xie, and N. Kocaman, "A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax & fiber," in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 127-130.
8 T. Ellermeyer, U. Langmann, B. Wedding, and W. Pohlmann, "A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver," in Proc. IEEE Int. Solid-State Circuits Conf., 2000, pp. 50-51.
9 X.F. Lin and J. Liu, "A Digital Power Spectrum Estimation Method for the Adaptation of High-speed Equalizer," IEEE Transactions on Circuits and Systems I, vol. 51, pp. 2436-2443, Dec. 2004.   DOI
10 D. Hernandez-Garduno, Jose Silva-Martinez, "A CMOS 1Gb/s 5-Tap Transversal Equalizer based on Inductor-Less Third-Order Delay Cells", to be presented in ISSCC Feb. 2007.
11 S. Gondi, "A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications," IEEE ISSCC Dig. Tech. Papers, Feb.2004, pp. 328-329.
12 J.-S. Choi et al., "A 0.18um CMOS 3.5Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method," IEEE J. Solid-State Circuits, pp. 419-425, March, 2004.
13 A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M. A. Horowitz, "Common-mode Backchannel Signaling System for Differential High-speed Links," IEEE Symposium on VLSI Circuits, June 2004.
14 Charles E. Berndt, Tad A. Kwasniewski: A Review of Common Receive-End Adaptive and Algorithms for a High-Speed Serial Backplane. IWSOC 2005: 149-153
15 Cathy Ye Liu, LSI Logic "Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps)" Designcon 2007, SantaClara,CA