• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.107-110
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• 2005

This paper describes the design and fabrication of synchronous clock recovery module for S-DMB Gap Filler. Using the 2.304MHz TTL signal from gap filler tuner, clock recovery module with 10MHz output frequency including holdover function is designed. The measured performance of the clock recovery module shows a stability of less than 0.01ppm, 29 sec stability time, 10 sec holdover time, and maximum -113dBc/Hz@100Hz phase noise.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• ETRI Journal
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• v.33 no.6
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• pp.841-848
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• 2011

A signal-to-noise ratio (SNR) enhancement algorithm using multiple chirp symbols with clock drift is proposed for accurate ranging. Improvement of the ranging performance can be achieved by using the multiple chirp symbols according to Cramer-Rao lower bound; however, distortion caused by clock drift is inevitable practically. The distortion induced by the clock drift is approximated as a linear phase term, caused by carrier frequency offset, sampling time offset, and symbol time offset. SNR of the averaged chirp symbol obtained from the proposed algorithm based on the phase derotation and the symbol averaging is enhanced. Hence, the ranging performance is improved. The mathematical analysis of the SNR enhancement agrees with the simulations.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.177-178
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• 2005

Wireless 1394 over IEEE802.15.3 must allow a data reserved for delivery over a wired 1394 network to be delivered over an IEEE802.15.3 wireless network through bridging IEEE 1394 to IEEE802.15.3. Isochronous transfers on the 1394 bus guarantee timely delivery of data. Specifically, isochronous transfers are scheduled by the bus so that they occur once every $125\;{\mu}s$ and require clock time synchronization to complete the real-time data transfer. IEEE1394.1 and Protocol Adaptation Layer for IEEE1394 over IEEE802.15.3 specify clock time synchronization for a wired 1394 bus network to a wired 1394 bus network and wireless 1394 nodes, which are IEEE802.15.3 nodes handling 1394 applications, over IEEE802.15.3. Thus, the clock time synchronizations are just defined within a homogeneous network environment like IEEE1394 or IEEE802.15.3 until now. This paper proposes new clock time synchronization method for wireless 1394 heterogeneous networks between 1394 and 802.15.3. If new method is adopted for various wireless 1394 products, consumer electronics devices such as DTV and Set-top Box or PC devices on a 1394 bus network can transmit real time data to the AV devices on the other 1394 bus in a different place via IEEE 802.15.3.

• Journal of Positioning, Navigation, and Timing
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• v.9 no.3
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• pp.261-272
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• 2020

A Kalman filter algorithm is used for the generation of an ensemble timescale with three hydrogen masers maintained in KRISS. Allan deviation curves of three pairs of clocks were obtained by a three-cornered hat method and were used as reference curves for determination of parameters of the Kalman filter-based timescale. The ensemble timescale equation of a 3-clock system was established, and the clocks' phases estimated by the Kalman filter were used as the prediction time of each clock in the equation. The weight of each clock was determined inversely proportional to the Allan variance calculated with the clocks' phases. The Allan deviation of the weighted mean was 1.2×10^-16 at the averaging time of 57,600 s. However when we made fine adjustments of the clocks' weight, the minimum Allan deviation of 2×10^-17 was obtained. To find out the reason of the great improvement in the frequency stability, additional researches are in progress theoretically and experimentally.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.85-88
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• 2000

This paper describes a Band-Selective Charge-Pump PLL(CPPLL) for clock recovery and clock generator. The proposed PLL satisfies fast acquisition time and low jitter characteristics simultaneously by reducing initial frequency error. The acquisition time of the designed Band-Selective CPPLL can be decreased down to 55% of a conventional CPPLL.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.702-706
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• 1996

The King Sejong's Striking water-clock was named for its distictive day and night time announcing system. Its time announcing system generates acoustic and visual signals for the twelve double hour, and combinations of two different acoustic signals for the five night watches, The mechanism of this signal generation system is triggered by a copper ball which is mechanically digitized time keeping signal, and is generated from the water clock. The time announcing system consisted four parts: 1) the mechanical amplifier which changes small copper to heavy steel ball, 2) day time announcing system, 3) night time announcing system, 4) sounding mechanism. The time announcing system of King Seong's Striking Clepsidra is remotely related to the Arabic clock system, however, it does have world-widely distictive mechanisms of its era, such as mechanical amplifier, self-weight rachet mechanism, and resetable mechanical computer etc.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.7-14
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• 2011

Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.7
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• pp.785-797
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• 2014

Support for the precise time synchronization of EtherCAT, known as distributed clock (DC), enables the design of highly synchronized operations in distributed real-time systems. This study evaluates the performance of the EtherCAT DC through extensive experiments in a real automation system. We constructed an EtherCAT control system using Xenomai and IgH EtherCAT stack, and analyzed the clock deviation for different devices in the network. The results of the evaluation revealed that the accuracy of the synchronized clock is affected by several factors such as the number of slave devices, period of drift compensation, and type of system time base. In particular, we found that careful decision regarding the system time base is required because it has a fundamental effect on the master operation, which results in significantly different performance characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.889-895
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• 2019

It is not easy to keep time promises in the complex daily lives. Especially, the increase in the number of vehicles causes traffic congestion in commuting time, which results in the delayed arrival and varies greatly depending on the weather conditions. In this paper, proposed is a smart alarm clock that automatically adjusts the alarm time according to weather conditions and suggests ways to deal with traffic congestion. The proposed smart alarm clock is designed to operate the functions of a normal alarm clock using touch functionality. In addition, it is designed to find weather information using open API and to automatically change alarm time to prepare for expected time delay. The proposed design was implemented based on Arduino Mega2560 and a touch TFT-LCD. WiFi module for internet connection, RTC module for clock function and MP3 player module for alarm sound playback were used together. The proposed design has been filed as a patent and is currently under review.