• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.165-176
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• 2015

Clock or time synchronization protocol is one of the crucial factors that could determine the quality of the communication. With the rapid development of the network technology, more robust clock synchronization algorithm is required. IEEE 1588 is one of the possible solutions for a robust clock synchronization algorithm; however, there are still some challenges that need to be concerned in IEEE 1588 in term of reducing and stabilizing the PDV value. This survey paper shows several solutions that could improve the performance of IEEE 1588, including modifying the PTP message transmission, optimizing PTP method, filtering techniques, and using the hardware timestamp instead of application layer timestamp, and so on. Despite the improvement that is created with these techniques, the clock synchronization algorithm is still an open issue in the network communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.1004-1010
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• 2012

In this paper, we propose the algorithm which considers applying recently proposed clock synchronization techniques with quite high accuracy in a few wireless sensor networks researches to time synchronization algorithm for multi-static radar system and especially overcomes the limitation of previous theory, cannot be applied between nodes in non-line of sight (NLOS). Proposed scheme estimates clock skew and clock offset using recursive robust least M-estimator with information of time stamp observations. And we improve the performance of algorithm by tracking and suppressing the time delays difference caused by NLOS system. Futhermore, this paper derive the mean square error (MSE) to present the performance of the proposed estimator and comparative analysis with previous methods.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.4
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• pp.163-170
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• 2014

A pseudolite is used as a GPS backup system, and is also used for the purpose of indoor navigation and correction information transmission. It is installed on the ground, and transmits signals that are similar to those of a GPS satellite. In addition, in recent years, studies on the improvement of positioning accuracy using the pseudorange measurement of a pseudolite have been performed. As for the effect of the time synchronization error between a pseudolite and a GPS satellite, a time synchronization error of 1 us generally induces a pseudorange error of 300 m; and to achieve meter-level positioning, ns-level time synchronization between a pseudolite and a GPS satellite is required. Therefore, for the operation of a pseudolite, a time synchronization algorithm between a GPS satellite and a pseudolite is essential. In this study, for the time synchronization of a pseudolite, "a pseudolite time synchronization method using the time source of UTC (KRIS)" and "a time synchronization method using a GPS timing receiver" were introduced; and the time synchronization performance depending on the pseudolite time source and reference time source was evaluated by designing a software-based pseudolite time synchronization performance evaluation simulation platform.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of Positioning, Navigation, and Timing
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• v.10 no.3
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• pp.197-206
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• 2021

We compared two typical ensemble time scale algorithms; AT1 and Kalman filter. Four commercial atomic clocks composed of two hydrogen masers and two cesium atomic clocks provided measurement data to the algorithms. The allocation of relative weights to the clocks is important to generate a stable ensemble time. A 30 day-average-weight model, which was obtained from the average Allan variance of each clock, was applied to the AT1 algorithm. For the reduced Kalman filter (Kred) algorithm, we gave the same weights to the two hydrogen masers. We also compared the frequency stabilities of the outcome from the algorithms when the frequency offsets and/or the frequency drift offsets estimated by the algorithms were corrected or not corrected by the KRISS-made primary frequency standard, KRISS-F1. We found that the Kred algorithm is more effective to generate a stable ensemble time scale in the long-term, and the algorithm also generates much enhanced short-term stability when the frequency offset is used for the calculation of the Allan deviation instead of the phase offset.