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A Continuous-time Equalizer adopting a Clock Loss Tracking Technique for Digital Display Interface(DDI)  

Kim, Kyu-Young (Dept. of Electronics and Computer Eng., Korea University)
Kim, Gil-Su (Dept. of Electronics and Computer Eng., Korea University)
Shon, Kwan-Su (Program in Micro/Nano Systems, Korea University)
Kim, Soo-Won (Dept. of Electronics and Computer Eng., Korea University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.2, 2008 , pp. 28-33 More about this Journal
Abstract
This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.
Keywords
Continuous-time equalizer; clock loss tracking; bottom hold circuit; feedforward loop;
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