• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.19-27
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• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1015-1022
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• 2012

This paper deals with hardware design which unifies MD5 and HAS-160 hash algorithms. Two algorithms get a message with arbitrary length and process message blocks divided into 512 bits each time and output a hash code with a fixed length. MD5 ouputs a hash code of 128 bits and HAS-160 a hash code of 160 bits. The unified hash core designed has 32% of slices overhead compared to HAS-160 core. However, there is only a fixed message buffer space used. The unified hash core which run a step in one clock cycle operates at 92MHz and has performance which digests a message in the speed of 724Mbps at MD5 and 581Mbps at HAS-160 hash mode. The unified hash core which is designed can be applicable to the areas such as E-commerce, data integrity and digital signature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.586-594
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• 2003

X-Match algorithm is a lossless compression algorithm suitable for hardware implementation owing to its simplicity. It can compress 32 bits per clock cycle and is suitable for real time compression. However, as the bus width increases 64-bit, the compression unit also need to increase. This paper proposes the cooperative parallel X-Match (X-MatchCP) algorithm, which improves the compression speed by performing the two X-Match algorithms in parallel. It searches the all dictionary for two words, combines the compression codes of two words generated by parallel X-Match compression and outputs the combined code while the previous parallel X-Match algorithm searches an individual dictionary. The compression ratio in X-MatchCP is almost the same as in X-Match. X-MatchCP algorithm is described and simulated by Verilog hardware description language.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.862-872
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• 1998

In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.91-98
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• 2008

Domestic standard for Korean T-DMB includes MPEG-4 BSAC (Bit Sliced Arithmetic Coding) audio coding that has been established in 2003. This paper presents an implementation and optimization of MPEG-4 BSAC Audio Decoder on ARM926EJ-S processor. Tools and modules of the BSAC audio decoder were implemented with 32-bit fixed point operations. Further optimization was accomplished using ARM926EJ-S Inline Assembly. The optimization was based on the total number of multiplications and MAC (Multiply and Accumulation) operations causing most of core cycles of ARM926EJ-S, and also based on analysis of ARMv5 instructions. The result of optimization was evaluated on the basis of MIPS (Million Instruction per second). Implementation results show that BSAC bitstream at 96kbps can be decoded in real-time at 65MHz CPU clocks.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.