• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.8
• /
• pp.22-38
• /
• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.2
• /
• pp.102-106
• /
• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.2
• /
• pp.117-123
• /
• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.399-401
• /
• 1999

최근 컴퓨터 네트워크를 통한 화상회의, 화상전화 VOD 등과 같은 응용 프로그램들이 실시간 통신을 필요로 한다. 이러한 실시간 통신에 적합한 ATM은 유연한 통신 서비스와 높은 질의 서비스를 제공함으로서 차세대 통신 네트웍으로 기대가 되고 있다. ATM 네트웍 막에서 실시간 통신을 하기 위해서는 실시간 데이터들이 지연한계를 만족해야 한다. 만약 이러한 지연한계를 만족시키지 못할 경우에는 서비스의 질이 떨어지거나 아니면 데이터가 아예 필요가 없어지게 된다. 이미 실시간 통신을 하기 위해 Virtual Clock, Stop-and-Go, EDF 등에 많은 패킷 스위치 스케줄링 정책들이 개발 되어져 왔다. 그러나 이러한 스위치 스케줄링 정책들은 대부분 그 방법의 복잡성 때문에 실제로 ATM 상에서 적용시키기가 힘들다. 본 논문에서는 ATM 네트웍 망에서 화상 통신을 하기 위해 적합한 새로운 스위치 모델인 TCRM-DS를 제시한다. TCRM-DS는 기존의 TCRM 모델의 장점인 단순성과 효율성을 그대로 유지하면서 TCRM 모델의 단점인 비 실시간 데이터에 대한 비효율적 처리를 개선한 것이다.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.282-285
• /
• 2002

In this paper, we designed of low power system by using dynamic scaling. As an effective low-power design, dynamic voltage/frequency scaling recently has received a lot of attention. In dynamic frequency scheme, all execution cycles are driven by the clock frequency that switched frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and higher frequency operators to later steps. This algorithm assigned the frequency for each execution cycle then it adjusted the voltage associated with the frequency.

• Journal of the Korean Society for Aviation and Aeronautics
• /
• v.21 no.1
• /
• pp.8-14
• /
• 2013

As GNSS(Global Navigation Satellite System) is used in various filed, many countries establish GNSS system independently. But GNSS system has the limitation of accuracy and stability in stand-alone mode, because this system has error elements which are ionospheric delay, tropospheric delay, orbit ephemeris error, satellite clock error, and etc. For overcome of accuracy limitation, the DGPS(Differential GPS) and RTK(Real-Time Kinematic) systems are proposed. These systems perform relative positioning using the reference and user receivers. ETRI(Electronics and Telecommunications Research Institute) is developing precision navigation system in point of extension of GNSS usage. The precision navigation system is for providing the precision navigation solution to common users. If this technology is developed, GNSS system can be used in the fields which require precision positioning and control. In this paper, we introduce the precision navigation system and perform design and algorithm verification.

• Journal of Sensor Science and Technology
• /
• v.21 no.5
• /
• pp.389-393
• /
• 2012

A chaotic oscillator with light controllability was designed. The proposed chaotic oscillator consists of a photo sensor, two phase clock driven MOS switches, nonlinear function blocks for chaotic signal generation. SPICE circuit analysis using a 0.35 um CMOS process parameters was performed for its chaotic dynamics. And we confirmed that chaotic behaviors of the circuit can be controlled according to light intensity. By SPICE simulation, chaotic dynamics by time waveforms, frequency analysis was analyzed. SPICE results showed that proposed circuit can make various light-controlled chaotic signals.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.3
• /
• pp.7-13
• /
• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• English Language & Literature Teaching
• /
• v.7 no.1
• /
• pp.67-89
• /
• 2001

This paper is to introduce assorted features of a four-week English Immersion Program managed by Hongik English Language Institute for the first time in summer 2000. The program was aimed to provide English learners with the English simulation environment where everything was supposed to be English only. Thus being exposed exclusively to the English surroundings the clock around, the learners who had not had enough opportunities to use the language were able to attain a high motivation for speaking English, which eventually led to the increase of their general English language proficiency. Presenting merits and demerits of the curriculum and the overall management of the program, this paper plays a role in directing the program in a more improved way for the future and giving guidelines to other institutes where similar programs are under consideration.

• ETRI Journal
• /
• v.33 no.3
• /
• pp.407-414
• /
• 2011

In an effort to reduce energy consumption, research into adaptive power management in real-time systems has become widespread. In this paper, a novel dynamic voltage scaling scheme is proposed for multiprocessor systems. Based on the concept of the Nash bargaining solution, a processor's clock speed and supply voltage are dynamically adjusted to satisfy these conflicting performance metrics. In addition, the proposed algorithm is implemented to react adaptively to the current system conditions by using an adaptive online approach. Simulation results clearly indicate that the superior performance of the proposed scheme can strike the appropriate performance balance between contradictory requirements.