• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.11-16
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• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.1-8
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• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.23-29
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• 2014

Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.15 no.1
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• pp.7-16
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• 2009

The purpose of this study was to evaluate current packaging modules and design the most acceptable packaging module for domestic and international distribution systems. An optimum packaging module can reduce package costs as well as total distribution costs such as transport, materials handling and warehouse costs. Three different sizes of packaging modules, namely U-type($600{\times}500\;mm$), K -ype($550{\times}366\;mm$) and I-type($600{\times}400\;mm$), were evaluated in terms of the area efficiency and MOEs(measures of effectiveness) for the T-11($1100{\times}1100mm$) and T-12($1,200{\times}1,000\;mm$) pallets. The results showed that the U-type module could fit very well for both pallets and the area efficiency of each module was more than 99 percents. Area efficiency of K-and I-type modules was greatly affected by the pallet footprint dimensions. U-type module also performed better result from MOEs evaluation. Twenty sub-multiple sizes derived from the U-type module were suggested for the future development of the Korean and ISO standards on dimension of transport packages.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• Korean Journal of Food Science and Technology
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• v.41 no.3
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• pp.272-277
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• 2009

In this research, three dimensional mathematical models were developed to predict the shelf life of tofu packaged in a semi-rigid plastic container. A model combining oxygen transfer through the package and oxygen consumption within the package was considered. According to the results, the model simulations estimated that the number of microorganisms in the filled water was higher than that in the tofu, suggesting the shelf life of packaged tofu was not affected by the number of microorganisms in the tofu product, but rather by the number of organisms in the filled water. Additionally, the effects of the physical properties of the packaging material, such as oxygen permeability through the package, oxygen diffusion coefficient, the initial oxygen concentration in the filled water, and the depth of the filled water in the packaged tofu, were also observed.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.141-141
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• 2013

본 연구에서는 3차원 실장을 위한 TSV 충전 기술 중 Cu 전해도금에 대해 연구하였다. TSV에 Cu를 전해도금함에 있어서 도금액의 유기첨가제 유무에 따른 충전거동과 표면 도금 상태를 관찰하였다. 연구 결과 가속제, 억제제, 평활제로 구성 된 유기첨가제가 모두 첨가된 경우 도금 속가 가장 빨랐으며, 표면도 가장 고르게 형성된 것을 알 수 있었다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.375-379
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• 2002

본 논문에서는 수 만개이상의 미지수를 필요로 하는 복잡한 3차원 구조에서의 정전용량 추출을 위한 고속화 알고리즘(Fast mutilpole method)과 결합한 효과적인 적응 삼각요소 분할법(Adaptive triangular mesh refinement algorithm)을 제안하였다. 요소세분화과정은 초기요소로 전하의 분포를 구하고, 전하밀도가 높은 영역에서의 요소세분화를 수행하여 이루어진다. 제안된 방법을 이용하여 많은 미지수를 필요로 하는 IC packaging 구조에서의 정전용량을 추출하였다.