• Journal of IKEEE
• /
• v.20 no.3
• /
• pp.220-225
• /
• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.128-128
• /
• 2010

중적외선 영역은 장애물에 의해서 파장의 흡수가 거의 일어나지 않기 때문에 적외선 소자에서 널리 이용되고 있다. 현재 대부분의 중적외선 소자에는 HgCdTe (MCT)가 사용되고 있지만, 3성분계 화합물이 가지는 여러 문제를 가지고 있다. 반면에, 2성분계 화합물인 인듐안티모나이드 (InSb)는 중적외선 영역 ($3-5\;{\mu}m$) 파장 대에서 HgCdTe와 대등한 소자 특성을 나타냄과 동시에 낮은 기판 가격, 소자 제작의 용이성, 그리고 야전과 우주 공간에서 소자 동작의 안정성 때문에 HgCdTe를 대체할 물질로 주목을 받고 있다. InSb는 미국과 이스라엘과 같은 일부 선진국을 중심으로 연구가 되었지만, 국방 분야의 중요한 소자로 인식되었기 때문에 소자 제작에 관한 기술적인 내용은 국내에 많이 알려지지 않은 상태이다. 따라서 본 연구에서는 InSb 소자 제작의 기초연구로 절연막과 pn 접합 형성에 대한 연구를 수행하였다. 절연막의 특성을 알아보기 위해, InSb 기판위에 $SiO_2$와 $Si_3N_4$를 PECVD (Plasma Enhanced Chemical Vapor Deposition)로 증착을 하였다. 절연막의 계면 트랩 밀도는 77K에서 C-V (Capacitance-Voltage) 분석을 통하여 계산하였으며, Terman method 방법을 이용하였다.[1] $SiO_2$는 $120-200^{\circ}C$의 온도 영역에서 계면 트랩 밀도가 $4-5\;{\times}\;10^{11}cm^{-2}$범위를 가진 반면, $240^{\circ}C$의 경우 계면 트랩 밀도가 $21\;{\times}\;10^{11}cm^{-2}$로 크게 증가하였다. $Si_3N_4$는 $SiO_2$ 절연막에 비해서 3배 정도의 높은 계면 트랩 밀도 값을 나타내었으며. Remote PECVD 장비를 이용하여 $Si_3N_4$ 절연막에 관한 연구를 추가적으로 진행하여 $7-9\;{\times}\;10^{11}cm^{-2}$ 정도의 계면 트랩 밀도 값을 구할 수가 있었다. 따라서 InSb에 대한 절연막은 $200^{\circ}C$ 이하에서 증착된 $SiO_2$와 Remote PECVD로 증착 된 $Si_3N_4$가 적합하다고 할 수 있다. 절연막 연구와 더불어 InSb 소자의 pn 접합 연구를 진행하였다. n-InSb (100) 기판 ($n\;=\;0.2-0.85\;{\times}\;10^{15}cm^{-3}$ @77K)에 $Be^+$이온 주입하여 p층을 형성하여 제작 되었으며, 열처리 조건에 따른 소자의 특성을 관찰 하였다. $450^{\circ}C$에서 30초 동안 RTA (Rapid Thermal Annealing)공정을 진행한 샘플은 -0.1 V에서 $50\;{\mu}A$의 높은 암전류가 관찰되었으며, 열처리 조건을 60, 120, 180초로 변화하면서 소자의 특성 변화를 관찰하였다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.08a
• /
• pp.250-250
• /
• 2013

단일벽 탄소나노튜브(Single-walled nanotubes, SWNTs)는 나노스케일의 크기와 우수한 물성으로 인하여, 전자, 에너지, 바이오 분야로의 응용이 기대되고 있다. 특히 SWNTs의 직경을 제어하게 되면 튜브의 전도성 제어가 훨씬 수월하게 되어, 차세대 나노전자소자의 실현을 앞당길 수 있으며 이러한 이유로 많은 연구들이 현재 행해지고 있다. SWNTs의 직경제어 합성을 위해서는 현재 열화학기상증착법(Thermal chemical vapor deposition; TCVD)이 가장 일반적으로 이용되고 있으며, 합성 촉매와 합성되는 튜브의 직경과의 크기 연관성이 알려진 후로는, 촉매의 크기를 제어하여 SWNTs의 직경을 제어하고자 하는 연구들이 활발하게 보고되고 있다. 특히, 촉매 나노입자의 직경이 1~2 nm 이하로 감소될 경우, SWNTs의 직경 분포가 어떻게 변화할 것인지가 최근 가장 중요한 관심사로 남아 있으나, 이러한 크기의 금속입자는 나노입자의 융점저하 현상이 발현되는 영역이므로, SWNTs의 합성온도 영역에서 촉매 금속입자는 반액체(Semi-liquid) 상태로 존재할 것으로 추측하고 있다. 본 연구에서는 고온의 SWNTs 합성환경에서 금속나노촉매의 유동성을 제한하기 위하여 나노사이즈의 기공이 규칙적으로 정렬된 다공성 물질인 제올라이트를 촉매담지체로 이용하였고, 이 때 다양한 합성변수가 SWNTs의 직경에 미치는 영향을 살펴보고자 하였다. SWNTs의 합성을 위해 실리콘 산화막 기판 위에 제올라이트를 도포한 후, 합성 촉매로서 전자빔증발법을 통하여 수 ${\AA}$에서 수 nm 두께의 철 박막을 증착하였다. 합성은 메탄을 원료가스로 하여 TCVD법으로 실시하였다. 주요변수로는 제올라이트 종류, 증착하는 철 박막의 두께, 합성온도를 설정하였으며, 이에 따라 합성된 SWNTs의 합성수율 및 직경분포의 변화를 체계적으로 살펴보았다. SWNTs의 전체적인 합성수율의 변화는 SEM 관찰결과를 이용하였으며, SWNTs의 직경은 AFM 관찰 및 Raman 스펙트럼의 분석에서 도출하였다. 실험결과, 제올라이트 종류에 따라서는 명확한 튜브직경 분포의 변화 없이 비교적 좁은 직경분포를 갖는 SWNTs가 합성되었으며, 합성온도가 $850^{\circ}C$ 이하로 감소되면 합성수율이 현저히 감소되는 것을 알 수 있었다. 촉매박막의 두께가 1 nm 이상인 경우에서는 직경 5 nm 전후의 나노입자가 형성되었으며, 이때 SWNTs의 합성수율은 높았으나 다양한 직경의 튜브가 합성이 된 것을 확인할 수 있었다. 반면, 촉매입자의 크기가 2 nm 이하에서는 합성수율은 다소 저하되었으나, SWNTs의 직경분포의 폭이 상대적으로 훨씬 좁아지는 것을 알 수 있었다. 추후, 극미세 촉매와 저온합성 환경에서의 합성수율 향상을 위한 합성공정의 개량이 지속적으로 요구된다.

• Korean Journal of Metals and Materials
• /
• v.46 no.11
• /
• pp.762-769
• /
• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Korean Journal of Metals and Materials
• /
• v.47 no.5
• /
• pp.322-329
• /
• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.16 no.3
• /
• pp.443-450
• /
• 2021

After selecting a PES substrate with excellent thermal stability and optical properties among plastic substrates, a SiO₂ thin film was deposited as a buffer layer to a thickness of 20nm by plasma-enhanced chemical vapor deposition to compensate for the high moisture absorption. Then, the ITZO thin film was deposited by a RF magnetron sputtering method to investigate electrical and optical properties according to RF power. The ITZO thin film deposited at 50W showed the best electrical properties such as a resistivity of 8.02×10^-4 Ω-cm and a sheet resistance of 50.13Ω/sq.. The average transmittance of the ITZO thin film in the visible light region(400-800nm) was relatively high as 80% or more when the RF power was 40 and 50W. Figure of Merits (Φ_TC and FOM) showed the largest values of 23.90×10^-4 Ω^-1 and 5883 Ω^-1cm^-1, respectively, in the ITZO thin film deposited at 50W.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.174-175
• /
• 2012

(In, Ga) N-based III-nitride semiconductor materials have been viewed as the most promising materials for the applications of blue and green light emitting devices such as light-emitting diodes (LEDs) and laser diodes. Although the InGaN alloy can have wide range of visible wavelength by changing the In composition, it is very hard to grow high quality epilayers of In-rich InGaN because of the thermal instability as well as the large lattice and thermal mismatches. In order to avoid phase separation of InGaN, various kinds of structures of InGaN have been studied. If high-quality In-rich InGaN/GaN multiple quantum well (MQW) structures are available, it is expected to achieve highly efficient phosphor-free white LEDs. In this study, we proposed a novel InGaN double hetero-structure grown on GaN nano-pyramids to generate broad-band red-color emission with high quantum efficiency. In this work, we systematically studied the optical properties of the InGaN pyramid structures. The nano-sized hexagonal pyramid structures were grown on the n-type GaN template by metalorganic chemical vapor deposition. SiNx mask was formed on the n-type GaN template with uniformly patterned circle pattern by laser holography. GaN pyramid structures were selectively grown on the opening area of mask by lateral over-growth followed by growth of InGaN/GaN double hetero-structure. The bird's eye-view scanning electron microscope (SEM) image shows that uniform hexagonal pyramid structures are well arranged. We showed that the pyramid structures have high crystal quality and the thickness of InGaN is varied along the height of pyramids via transmission electron microscope. Because the InGaN/GaN double hetero-structure was grown on the nano-pyramid GaN and on the planar GaN, simultaneously, we investigated the comparative study of the optical properties. Photoluminescence (PL) spectra of nano-pyramid sample and planar sample measured at 10 K. Although the growth condition were exactly the same for two samples, the nano-pyramid sample have much lower energy emission centered at 615 nm, compared to 438 nm for planar sample. Moreover, nano-pyramid sample shows broad-band spectrum, which is originate from structural properties of nano-pyramid structure. To study thermal activation energy and potential fluctuation, we measured PL with changing temperature from 10 K to 300 K. We also measured PL with changing the excitation power from 48 ${\mu}W$ to 48 mW. We can discriminate the origin of the broad-band spectra from the defect-related yellow luminescence of GaN by carrying out PL excitation experiments. The nano-pyramid structure provided highly efficient broad-band red-color emission for the future applications of phosphor-free white LEDs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.31-31
• /
• 2010

The growth of the high-quality GaN epilayers is of significant technological importance because of their commercializedoptoelectronic applications as high-brightness light-emitting diodes (LEDs) and laser diodes (LDs) in the visible and ultraviolet spectral range. The GaN-based heterostructural epilayers have the polar c-axis of the hexagonal structure perpendicular to the interfaces of the active layers. The Ga and N atoms in the c-GaN are alternatively stacked along the polar [0001] crystallographic direction, which leads to spontaneous polarization. In addition, in the InGaN/GaN MQWs, the stress applied along the same axis contributes topiezoelectric polarization, and thus the total polarization is determined as the sum of spontaneous and piezoelectric polarizations. The total polarization in the c-GaN heterolayers, which can generate internal fields and spatial separation of the electron and hole wave functions and consequently a decrease of efficiency and peak shift. One of the possible solutions to eliminate these undesirable effects is to grow GaN-based epilayers in nonpolar orientations. The polarization effects in the GaN are eliminated by growing the films along the nonpolar [$11\bar{2}0$] ($\alpha$-GaN) or [$1\bar{1}00$] (m-GaN) orientation. Although the use of the nonpolar epilayers in wurtzite structure clearly removes the polarization matters, however, it induces another problem related to the formation of a high density of planar defects. The large lattice mismatch between sapphiresubstrates and GaN layers leads to a high density of defects (dislocations and stacking faults). The dominant defects observed in the GaN epilayers with wurtzite structure are one-dimensional (1D) dislocations and two-dimensional (2D) stacking faults. In particular, the 1D threading dislocations in the c-GaN are generated from the film/substrate interface due to their large lattice and thermal coefficient mismatch. However, because the c-GaN epilayers were grown along the normal direction to the basal slip planes, the generation of basal stacking faults (BSFs) is localized on the c-plane and the generated BSFs did not propagate into the surface during the growth. Thus, the primary defects in the c-GaN epilayers are 1D threading dislocations. Occasionally, the particular planar defects such as prismatic stacking faults (PSFs) and inversion domain boundaries are observed. However, since the basal slip planes in the $\alpha$-GaN are parallel to the growth direction unlike c-GaN, the BSFs with lower formation energy can be easily formed along the growth direction, where the BSFs propagate straightly into the surface. Consequently, the lattice mismatch between film and substrate in $\alpha$-GaN epilayers is mainly relaxed through the formation of BSFs. These 2D planar defects are placed along only one direction in the cross-sectional view. Thus, the nonpolar $\alpha$-GaN films have different atomic arrangements along the two orthogonal directions ($[0001]_{GaN}$ and $[\bar{1}100]_{GaN}$ axes) on the $\alpha$-plane, which are expected to induce anisotropic biaxial strain. In this study, the anisotropic strain relaxation behaviors in the nonpolar $\alpha$-GaN epilayers grown on ($1\bar{1}02$) r-plane sapphire substrates by metalorganic chemical vapor deposition (MOCVO) were investigated, and the formation mechanism of the abnormal zigzag shape PSFs was discussed using high-resolution transmission electron microscope (HRTEM).

• Journal of the Korean Vacuum Society
• /
• v.17 no.6
• /
• pp.528-537
• /
• 2008

60 nm and 20 nm thick hydrogenated amorphous silicon(a-Si:H) layers were deposited on 200 nm $SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by an e-beam evaporator. Finally, 30 nm-Ni/(60 nm and 20 nm) a-Si:H/200 nm-$SiO_2$/single-Si structures were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 40 sec. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide from the 60 nm a-Si:H substrate showed low sheet resistance from $400^{\circ}C$ which is compatible for low temperature processing. The nickel silicide from 20 nm a-Si:H substrate showed low resistance from $300^{\circ}C$. Through HRXRD analysis, the phase transformation occurred with silicidation temperature without a-Si:H layer thickness dependence. With the result of FE-SEM and TEM, the nickel silicides from 60 nm a-Si:H substrate showed the microstructure of 60 nm-thick silicide layers with the residual silicon regime, while the ones from 20 nm a-Si:H formed 20 nm-thick uniform silicide layers. In case of SPM, the RMS value of nickel silicide layers increased as the silicidation temperature increased. Especially, the nickel silicide from 20 nm a-Si:H substrate showed the lowest RMS value of 0.75 at $300^{\circ}C$.