• 국제물리치료학회지
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• 제6권2호
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• pp.902-907
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• 2015

The purpose of this study was to parallel circuit training and circuit training with sonic systemic mechanism was to compare the differences in pulmonary function and chest expansion in adult men. This study was performed on 20 subjects. 20 subjects were divided into two groups; Circuit training group(n=10), Circuit training with sonic systemic mechanism(n=10). Both of the group performed the exercise 3 times a week for 5 weeks. The data was analyzed by the Repeated t-test for comparing before, during and after changes of factors in each group and the Independent t-test for comparing the between groups. The result are as follows. Circuit training group was statistically significant difference FVC, FEV1/FVC(p<.05), Circuit training with sonic systemic mechanism group was statistically significant difference PEF, VC in pulmonary function(p<.05). Circuit training group was statistically significant difference FEV1/FVC of between the two group in pulmonary function(p<.05). Circuit training group and circuit training with sonic systemic mechanism group was statistically significant difference in chest expansion(p<0.05) and there was no statistically significant difference of between the two group in chest expansion(p>.05).

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.404-408
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• 2003

The characterization for several multi-layer embedded inductors with different structures was investigated. The optimized equivalent circuit models for several test structures were obtained from HSPICE. Building blocks are modeled using Partial element equivalent circuit method. The mean and the standard deviation of model parameters were extracted and predictive modeling was performed on different test structure. From this study, the characteristic of multi-layer inductors can be predicted.

• 대한전자공학회논문지
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• 제24권3호
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• pp.517-526
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• 1987

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.882-885
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• 2011

This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.130-133
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• 2004

The characterization of interdigitated capacitors was investigated. The test structures are manufactured by low temperature co-fired ceramic(LTCC) process and their s-parameters were measured. The optimized equivalent circuit models for test structures were obtained using the partial element equivalent circuit(PEEC) method. Predictive modeling was performed on different test structures using optimized parameters to verify the circuit models. From this result, the manufacturability on the process can be improved through the predictive modeling for the characteristics of interdigitated capacitors.

• 제어로봇시스템학회논문지
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• 제3권3호
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• pp.323-331
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• 1997

A new probing mechanism and an active compliance control algorithm have been developed for the in-circuit test of a PCB( printed circuit board ). Commercially available robotic probing devices are incapable of controlling contact force generated through rigid probe contacts with a solder joint, at high speed. The uncontrollable excessive contact force often brungs about some defects on the surface of the solder joint, which is plastically deformable over some limited contact force. This force also makes unstable contact motions resulting in unreliable test data. To overcome these problems, we propose that a serially connected macro and micro device with active compliance provide the best potential for a safe and reliable in-circuit test. This paper describes the design characteristics, modeling and control scheme of the newly proposed device. The experimental results clearly show the effectiveness of the proposed system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.554-556
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• 2004

Testing capacity of KERI synthetic short-circuit testing facilities has been upgraded to fulfill the requirements up to 550kV 63kA, 1-break circuit breaker ratings. Specially the current capacity was increased 50kA to 63kA and the full type test of 362kV 63kA circuit breaker(1-break) was firstly completed in domestic. UP to now, domestic manufacturers have depended on the foreign testing laboratory for performance verification of newly designed products. This paper introduces the summary of the increased short-circuit testing facilities, the testing techniques and its results for the making and breaking performance of 362kV, 63kA circuit breaker which was Performed according to IEEE C37.06(1999) used in North America.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.49-56
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• 2005

본 논문에서는 사용자로부터 테스트하고자 하는 고장 모델을 입력받아 적절한 much 테스트 알고리즘을 만들고 BIST 회로를 생성해 주는 Memory BIST Circuit Creation System(MBCCS) 을 제안하고 있다. 기존의 툴들은 널리 사용되고 있는 알고리즘에 국한되어 메모리의 사양이 변할 경우 거기에 맞는 BIST 회로를 다시 생성해주는 번거로움이 있었다. 하지만 본 논문에서 제안한 툴에서는 다양해진 메모리 구조에 적합한 메모리 BIST 회로를 사용자 요구에 맞는 알고리즘을 적용해서 자동적으로 생성하게 하였고, 임의적으로 선택된 고장 모델에 대한 알고리즘을 제안된 규칙에 따라 최적화함으로 해서 효율성을 높였다. 또한 다양한 크기의 폭을 갖는 주소와 데이터를 지원하며 IEEE 1149.1 회로와의 인터페이스도 고려하였다.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.286-292
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• 2014

This paper presents the parameters optimization technology for generating the first short stroke lightning current waveform($10/350{\mu}s$) which is necessary for the performance tests of components of lightning protection systems, as required under IEC 62305 and the newly amended IEC 62561. The circuit using the crowbar device specified in IEC 62305 was applied to generate the lightning current waveform. To find the proper parameters of the circuit is not easy because the circuit consists of two parts; circuit I, which relates to the front of current waveform, and circuit II, which relates to the tail. A simulation in PSpise was carried out to find main factors related to the front and tail of $10/350{\mu}s$. The lightning current generator was developed by utilizing the circuit parameters found in the simulation. In the result of experiments, new parameters of the circuits need to be changed because of the difference between the simulation and the experiment results. Using the iterative method, the optimized parameters of the circuits was determined. Also a multistage-type external coil and a damping resistor were proposed to make the efficiency of generation to enhance. According to the result in this paper, an optimized first short stroke lightning current waveform was obtained.

• 한국산업융합학회 논문집
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• 제25권3호
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• pp.333-340
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• 2022

Recently, the use of large-capacity secondary batteries for electric vehicles is rapidly increasing, and accordingly, the demand for technologies and equipment for battery reliability evaluation is increasing significantly. The existing short circuit test equipment for evaluating the stability of the existing secondary battery consists of relays, MCs, and switches, so when a large current is energized during a short circuit, contact fusion failures occur frequently, resulting in high equipment maintenance and repair costs. There was a disadvantage that repeated testing was impossible. In this paper, we developed an electronic short circuit test device that realizes stable switching operation when a large-capacity power semiconductor switch is energized with a large current, and applied smart ICT technology to this electronic short circuit stability test system to achieve high speed and high precision through communication with the master. It is expected that the inspection history management system based on data measurement, database format and user interface will be utilized as essential inspection process equipment.