• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.1-8
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• 2009

Since scan based testing is very efficient and widely used for testing large sequential circuits. However, since test patterns are serially injected through long scan chains, scan based testing requires very long test application time. Also, compared to the normal operations, scan shifting operations drastically increase power consumption. In order to solve these problems, this paper presents a new scan architecture for both test application time and test power reduction. The proposed scan architecture partitions scan chains into several segments and bypasses some segments which do not include any specified bit. Since bypassed segments are excluded from the scan shifting operation, the test application time and test power can be significantly reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.41-50
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• 2005

As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• International Journal of Highway Engineering
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• v.15 no.4
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• pp.85-94
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• 2013

PURPOSES: The performance of tack coat, commonly used for layer interface bonding, is affected by application rate and curing time. In this study, bonding strength tests were performed according to the application rate and curing time of asphalt emulsion. Based on finding from this study, optimum application rates and curing times are proposed. METHODS: In order to investigate bonding characteristic of asphalt emulsion, tests were performed on both asphalt concrete pavement and portland concrete pavement. Also, asphalt emulsions were tested at the application rate of 0, 0.2, 0.4, 0.6, and $0.8{\ell}/m^2$ and at the curing time of 0, 0.5, 1, 2, and 24 hours. Pull-off test and shear bonding strength test, which commonly used for bonding strength measurement of asphalt emulsion, were adopted for this study. To assess field performance under different testing condition, asphalt emulsions were applied to in-service pavement. Throughout coefficient of determination analysis between material index properties from asphalt emulsion and mechanical response from bonding strength tests, performance correlativity was analyzed. RESULTS: Test results show that optimum application rate for asphalt overlay on asphalt concrete pavement (AOA) and asphalt overlay on concrete pavement (AOC) was $0.4{\sim}0.5{\ell}/m^2$ and $0.3{\sim}0.5{\ell}/m^2$, respectively. According to the curing time increment, tensile strength and shear strength of AOC were increased to 22~44% and 20~39%, respectively. AOA case also show strength increment in tensile strength (42%) and shear strength (9%). We tested the applicability of tack coat materials at the field sites, and our findings demonstrated that the bonding (for D and E) and rapid curing (for B, C, and D, E) performances were superior than others. Among material index properties, there was a high correlation between penetration ratio and bonding strength test result. CONCLUSIONS : Result show that interlayer bonding strength was affected by asphalt emulsion type, application rate and curing time. AOC required slightly higher application ($0.1{\ell}/m^2$) than AOA. Both AOA and AOC cases show higher strength at longer curing time. Up to 2hours of curing, rapid strength increments were observed, but strength increment ratio was decreased after 2hours of curing. From the observed correlation between penetration ratio and bonding strength, it is expected that penetration ratio can be used as one of important factors affecting bonding strength analysis.

• International Journal of Highway Engineering
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• v.18 no.5
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• pp.1-9
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• 2016

PURPOSES : This study focuses on the evaluation of interface performance with varying surface texture and tack coat application in an asphalt overlay. METHODS : The evaluation is carried out in two phases: tracking test and interface bond strength test. Using an image processing tool, tracking test is conducted to evaluate the susceptibility of the tack coat material to produce excessive tracking during application. Using the pull-off test method, the bond strength test is performed to determine the ability of the interface layer to resist failure. RESULTS : Results show that the underseal application yields less tracking compared to other applications. However, the bond strength is barely within the minimum acceptable value. On the other hand, RSC-4 produces higher bond strength for all surface types, but the drying time is long, which produces excessive tracking. CONCLUSIONS : While underseal application may be suitable for a trackless condition, the bond strength is less appealing compared to the rest of the tack applications available. RSC-4 demonstrated a high and consistent bond strength performance, but more time is required for drying to avoid excessive tracking. Tack coat application and surface type combination produce varying results. Therefore, these should be considered when selecting suitable future tack coat application options.

• Journal of the Korean Society for Heat Treatment
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• v.13 no.1
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• pp.10-15
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• 2000

Evaluation of long term stability of the Brinell standard hardness tester was carried out to secure its application as a national standard in Brinell hardness. Accuracy and repeatability in load application were tested through evaluating errors in hardness measurement of certified reference blocks. All of those requirements in KS as well as ISO specifications were satisfied by this standard hardness tester. In addition to this, long term stability test of automatic indentation measurement system was carried out. The scattering range was almost the same with its error range. To figure out an optimum test condition for better repeatability and long term stability, the effect of load variation, load application speed and time have been studied using orthogonal array experimental plan. It was found that the best combination is $30{\mu}m/s$ of load application speed and 25 seconds of load application time.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.2063_2064
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• 2009

Recently, load circuits and components of customer are various. Therefore failures of ELB(Earth Leakage Breaker) and MCCB(Molded case circuit breakers) are more frequent. Lite time of MCCB even if there is same units differ from environment, condition of operation. FEMCA is a efficiency method of system operation or maintenance for system reliability. We study on FMECA procedures and method. In this paper, we focused on FMECA application to MCCB life time test.

• Journal of the Korean Data and Information Science Society
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• v.17 no.1
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• pp.115-122
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• 2006

A test is suggested for detecting deviations from both multivariate normality and independence. This test can be used for assessing the normality and independence of univariate time series residuals. We derive the limiting distribution of the test statistic and a simulation study is conducted to study the accuracy of the limiting distribution in finite samples. Finally, we apply our method to a real data of time series.