Browse > Article

SMC: An Seed Merging Compression for Test Data  

Lee Min-joo (Department of Electrical Electronic School, Yonsei University)
Jun Sung-hun (Department of Electrical Electronic School, Yonsei University)
Kim Yong-joon (Department of Electrical Electronic School, Yonsei University)
Kang Sumg-ho (Department of Electrical Electronic School, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.9, 2005 , pp. 41-50 More about this Journal
Abstract
As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.
Keywords
seed; reuse; merging; prefix codes; XOR network;
Citations & Related Records
연도 인용수 순위
  • Reference
1 A. Jas, B. Pouya, and N. A. Touba, 'Virtual scan chains: A means for reducing scan length in cores,' Proceedings of IEEE VLSI Test Symposium, pp. 73 - 78, 2000   DOI
2 A. El-Maleh, S. al Zahir, and E. Khan, 'A geometric-primitives-based compression scheme for testing systems-on-a-chip,' Proceedings of IEEE VLSI Test Symposium, pp. 49 - 54, 2001   DOI
3 Ismet Bayraktaroglu and Alex Orailoglu, 'Concurrent application of compaction and compression for test time and data volume reduction in scan designs,' IEEE Transactions on Computers, vol. 52, NO. 11, pp. 1480 - 1489, 2003   DOI   ScienceOn
4 I. Hamzaoglu and J. H. Patel, 'Reducing test application time for full scan embedded cores,' Proceedings of IEEE International Symposium Fault-Tolerant Computing, pp. 260 - 267, 1999   DOI
5 C. V. Krishna, Abhijit Jas, and Nur A. Touba. 'Test vector encoding using partial LFSR reseeding,' Proceedings qf International Test Conference, pp. 885 - 893, 2001   DOI
6 A. Chandra and K. Chakrabarty, 'System-on-a-Chip test data compression and decompression architectures based on golomb codes,' Proceedings of International Conference on Computer Aided Design, vol. 20, n. 3, pp. 355 - 368, 2001   DOI   ScienceOn
7 S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, 'Built-in Test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers,' IEEE Transactions on Computers, vol. 44, n. 2, pp. 223 - 233, 1995   DOI   ScienceOn
8 I. Bayraktaroglu and A. Orailogu, 'Test volume and application time reduction through scan chain concealment,' Proceedings of The Design Automation Conference, pp. 151 - 155, 2001
9 Wenjing Rad and Ismet Bayraktaroglu and Alex Orailoglu, 'Test application time and volume compression through seed overlapping,' Proceedings of The Design Automation Conference, pp. 732 - 737, 2003
10 A. Jas, J. Ghosh-Dastidar and N. A. Touba, 'Scan vector compression/decompression using statistical coding,' Proceedings of VLSI Test Symposium, pp. 25 - 29, 1999
11 Anshuman Chandra and Krishnendu Chakrabarty, 'Test data compression and test resource partitioning for System-on-a chip using frequency-directed run-length (FDR) Codes,' IEEE Transactions on Computers, vol. 52, pp. 1076 - 1088, 2003   DOI   ScienceOn
12 R. Sankaralingam, R. Oruganti, and N. A. Touba, 'Static compaction techniques to control scan vector power dissipation,' Proceedings of VLSI Test Symposium, pp. 35 - 40, 2000   DOI
13 S. Bhatia and P. Varma, 'Test compaction in a parallel access scan environment,' Proceedings of Asian Test Symposium, pp. 300-305, 1997
14 I. Hamzaoglu and J. H. Patel, 'Test set compaction algorithms for combinational circuits,' Proceedings of International Test Conference, pp. 283-289, 1998
15 I. Pomeranz and S. M. Reddy, 'Static test compaction for scan based designs to reduce test application time,' Proceedings of Seventh Asian Test Symposium, pp. 198 - 203, 1998
16 C. V. Krishna and Nur A. Touba, 'Adjustable width linear combinational scan vector decompression,' Proceedings of International Conference on Computer Aided Design, pp. 863-866, 2003   DOI
17 Hideyuki Ichihara and Kozo Kinoshita and Koji Isodono, 'Channel width test data compression under a limited number of test inputs and outputs,' Proceedings of the 16th International Conference on VLSI Design, pp. 329 - 334, 2003   DOI
18 I. Hamzaoglu and J. H. Patel, 'Reducing test application time for Built-In-Self-Test test pattern generators,' Proceedings of IEEE VLSI Test Symposium, pp. 260 - 267, 1999
19 Y. Zorian, S. Dey and M. J. Rodgers, 'Test of future system on chips,' Proceedings of International Conference on Computer Aided Design, pp. 392-400, 2000   DOI