• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 전기의세계
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• v.28 no.1
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• Journal of Applied and Pure Mathematics
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• v.6 no.1_2
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• pp.97-103
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• 2024

This study is about digits of numbers in system logic B₃. Any real number is written as digits in the binary system, in the ternary system. The numbers in base two and base three are also written in the B₃ system ternary logic. These two writing methods are transferred into the third method. The real numbers 0,1 and 0, 1, 2 are written as digits. The same real numbers are written as digits of elements of the set -1, 0, 1 in base B₃. The periods here are investigated. The relationship between these digits is analysed.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.152-157
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• 2024

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Journal of Applied and Pure Mathematics
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• v.5 no.3_4
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• pp.187-196
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• 2023

This study is about spin half add operations in 𝓑₂ and 𝓑₃. The burden of technological structures has increased due to the increase in the use of today's technological applications or the processes in the digital systems used. This has increased the importance of fast transactions and storage areas. For this, less transactions, more gain and storage space are foreseen. We have handle tit (triple digit) system instead of bit (binary digit). 729 is reached in 3⁶ in 𝓑₃ while 256 is reached with 2⁸ in 𝓑₂. The volume and number of transactions are shortened in 𝓑₃. The limited storage space at the maximum level is storaged. The logic connectors and the complement of an element in 𝓑₂ and the course of the connectors and the complements of the elements in 𝓑₃ are examined. "Carry" calculations in calculating addition and "borrow" in calculating difference are given in 𝓑₃. The logic structure 𝓑₂ is seen to embedded in the logic structure 𝓑₃. This situation enriches the logic structure. Some theorems and lemmas and properties in logic structure 𝓑₂ are extended to logic structure 𝓑₃.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.