• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 ITC-CSCC -1
• /
• pp.347-350
• /
• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 전기의세계
• /
• 제28권1호
• /
• pp.43-52
• /
• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• Journal of Applied and Pure Mathematics
• /
• 제6권1_2호
• /
• pp.97-103
• /
• 2024

This study is about digits of numbers in system logic B₃. Any real number is written as digits in the binary system, in the ternary system. The numbers in base two and base three are also written in the B₃ system ternary logic. These two writing methods are transferred into the third method. The real numbers 0,1 and 0, 1, 2 are written as digits. The same real numbers are written as digits of elements of the set -1, 0, 1 in base B₃. The periods here are investigated. The relationship between these digits is analysed.

• 센서학회지
• /
• 제33권3호
• /
• pp.152-157
• /
• 2024

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.

• Journal of Semiconductor Engineering
• /
• 제1권1호
• /
• pp.57-63
• /
• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• 대한전자공학회논문지SD
• /
• 제44권1호
• /
• pp.36-44
• /
• 2007

본 논문은 Delay-Insensitive(DI) 지연 모델을 갖는 비동기식 회로에 3치 전압 레벨을 사용한 하이브리드 터너리 데이터 전송 방식을 제안하고, 이를 이용하여 다양한 비동기 프로토콜과의 데이터 송신 및 수신을 위한 래퍼를 설계하였다. 제안된 하이브리드 터너리 데이터 전송 방식은 기존의 2 선식 전송 방식이나 1-of-4 전송 방식에 비해 데이터 전송선을 50% 줄일 수 있으며, 터너리 전송 방식과 비교하였을 때도 50%의 신호 천이 감소 결과를 보였다. 본 논문에서는 $0.18-{\mu}m$ CMOS 공정을 적용하여 래퍼를 설계하고 검증하였다. 하이브리드 터너리 전송 방식이 적용된 래퍼는 2 GHz 이상의 속도로 동작 하였으며 2 선식, 1-of-4, 그리고 터너리 전송 방식에 비해 각각 65%, 43%, 36%의 소비 전력이 줄어든 결과를 보였다. 제안된 전송 방식과 설계된 래퍼 회로는 비동기식 고속 및 저전력 인터페이스로 사용 가능하다.

• Journal of Applied and Pure Mathematics
• /
• 제5권3_4호
• /
• pp.187-196
• /
• 2023

This study is about spin half add operations in 𝓑₂ and 𝓑₃. The burden of technological structures has increased due to the increase in the use of today's technological applications or the processes in the digital systems used. This has increased the importance of fast transactions and storage areas. For this, less transactions, more gain and storage space are foreseen. We have handle tit (triple digit) system instead of bit (binary digit). 729 is reached in 3⁶ in 𝓑₃ while 256 is reached with 2⁸ in 𝓑₂. The volume and number of transactions are shortened in 𝓑₃. The limited storage space at the maximum level is storaged. The logic connectors and the complement of an element in 𝓑₂ and the course of the connectors and the complements of the elements in 𝓑₃ are examined. "Carry" calculations in calculating addition and "borrow" in calculating difference are given in 𝓑₃. The logic structure 𝓑₂ is seen to embedded in the logic structure 𝓑₃. This situation enriches the logic structure. Some theorems and lemmas and properties in logic structure 𝓑₂ are extended to logic structure 𝓑₃.

• 융합신호처리학회논문지
• /
• 제9권1호
• /
• pp.54-61
• /
• 2008

본 논문에서는 디지털 신호를 실시간으로 처리하기 인한 TIQ 방식의 Flash 6-bit ADC 회로를 설계하였다. 새로운 논리회로 설계나 소자들의 근접 배치로 ADC의 속도를 향상시키는 대신에 새로운 코드를 이용하여 DSP의 처리능력을 높이도록 하였다. 제안한 코드는 ADC의 출력으로 이진수를 세공하지 않고 2와 3진법을 동시에 사용하는 Double Base Number System(DBNS)방법이다. 전압은 기존의 이진수를 표시하는 방법과 동일하지만, 밑수로 2와 3의 두개를 동시에 사용하여 합의 형태로 표현하는 방법이다. DBNS 표현법은 곱셈기와 가산기를 이용하지 않고 연산을 좌우로 이동하여 연산을 신속히 처리할 수 있다. 디지털 신호처리에서 사용하는 DBNS는 합의 수가 적도록 Canonical 표현을 구하는 알고리즘을 사용하지만, A/D 변환기에서는 Fan-In 문제가 발생하여 균일한 분포를 이루도록 하는 새로운 알고리즘을 개발하였다. HSPICE를 이용한 ADC의 시뮬레이션 결과 0.18um 공정에서 최고 동작속도는 1.6 GSPS이며 최대 소비전력은 38.71mW이였다.