• Proceedings of the KIEE Conference
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• summer
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• pp.842-844
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• 2004

The Back Up Breaker and Making Switch are very important equipments for the short circuit test facility, and contacts are the most important parts of the above switches. There are very many kind of contacts according to switches characteristic and should be done the verification test before use, especially development contacts. This study describes the class of switches, arc chute, material of whole contacts and essential test for verification. The essential test for verification are dielectric test, mechanical operation test, short-time withstand current test, load current breaking test, and short-circuit making current test etc.

• Journal of Power Electronics
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• v.12 no.5
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• pp.723-730
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• 2012

This paper presents a new ZVS single phase bridgeless (Power Factor Correction) PFC, using an active clamp to achieve zero-voltage-switching for all main switches and diodes. Since the presented PFC uses a bridgeless rectifier, most of the time, only two semiconductor components are in the main current path, instead of three in conventional single-switch configurations. This property significantly reduces the conduction losses,. Moreover, zero voltage switching removes switching loss of all main switches and diodes. Also, auxiliary switch turns on zero current condition. The presented converter needs just a simple non-isolated gate drive circuitry to drive all switches. The eight stages of each switching period and the design considerations and a control strategy are explained. Finally, the converter operation is verified by simulation and experimental results.

• Journal of Power Electronics
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• v.12 no.6
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• pp.859-868
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• 2012

In this paper, a novel bidirectional DC-DC converter employing soft switching technique was proposed. Compare to conventional bidirectional converters, the main switches of proposed converter are operated without switching losses. Moreover, auxiliary switches are used, and the switches are operated under zero voltage switching (ZVS) and zero current switching (ZCS) condition. To verify the validity of the proposed converter, mode analysis, design procedure, simulation and experimental results are presented.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.686-688
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• 1996

Network reconfiguration is performed by opening/closing two types of switches, tie and sectionalizing switches. A whole feeder, or part of a feeder, may be served from another feeder by closing a tie switch linking the two while an appropriate sectionalizing switch must be opened to maintain radial structures. In loss reduction, the problem is to identify tie and sectionalizing switches that should be closed and opened, respectively, to achieve a maximum loss reduction. In this paper, it is introduced to propose the reconfiguration plan for loss reduction by using the Civanlar's loss reduction formular.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.13-17
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• 2005

The link e daggregation between 10GbE switches requires an advanced framistribution method to be properly and efficiently applied. The fixed or dynamic frame distribution methods, formerly proposed, cannot fully utilize the aggregated links, where the receiving terminal only attaches to a pre-specified link among multiple physical links. A frame distribution method using padding is proposed for the link aggregation between 10GbE switches to solve this problem. We compared the performance of the proposed method with those of the static and dynamic frame distribution methods. As a result, the proposed method shows a better performance when the offered load is below 0.7 and the average length of the frames is longer than 954 bytes.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.15-16
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• 2012

This paper is study on a novel high efficiency step up-down converter using loss-less snubber capacitor. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.74-76
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• 2019

This paper proposes an open-switch fault tolerant strategy based on the model predictive control for a full bidirectional switches indirect matrix converter (FBS-IMC). Compared to the conventional Indirect Matrix Converter (IMC), the FBS-IMC can provide healthy current path when open-switch fault is occurred. To keep the continuous operation, the fault tolerant strategy is developed by means of reversing the DC-link voltage polarity regardless of the faulty switch location in the rectifier or inverter stage. Therefore, the proposed control strategy can maintain the same input and output performances during the faulty condition as the normal condition. The simulation results are given to verify the effectiveness of the proposed strategy.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.2
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• pp.733-750
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• 2019

Software Defined Networking (SDN) is a new network paradigm, allowing administrators to manage networks through central controllers by separating control plane from data plane. So, one or more controllers must locate outside switches. However, this separation may cause delay problems between controllers and switches. In this paper, we therefore propose a Priority-based Scheduling policy for OpenFlow (PSO) to reduce the delay of some significant traffic. Our PSO is based on packet prioritization mechanisms in both OpenFlow switches and controllers. In addition, we have prototyped and experimented on PSO using a network simulator (ns-3). From the experimental results, PSO has demonstrated low delay for targeted traffic in the out-of-brand control network. The targeted traffic can acquire forwarding rules with lower delay under network congestion in control links (with normalized load > 0.8), comparing to traditional OpenFlow. Furthermore, PSO is helpful in the in-band control network to prioritize OpenFlow messages over data packets.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.203-217
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• 2007

In this paper, a performance evaluation model of Networks with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch networks. The characteristic of a network with crossbar switches is determined by both the connection pattern of the switches and the limitation of data flow in a each switch. In this thesis, the evaluation models of three different networks : Multistage interconnection network, Fat-tree network, and other ordinary communication network are developed. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of networks that uses the multiple buffered crossbar switches. It is shown that both the analysis and the simulation results match closely. It is also observed that the increasing rate of Normalized Throughput is reduced and the Network Delay is getting bigger as the buffer size increased.