• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.345-347
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• 2000

This paper proses a soft-switching current-source inverter with a switched-capacitor module. The system operation was analyzed by a theoretical approach with equivalent circuits and verified by a computer simulation and experiment. The proposed system could be effectively applied for the power converter of photovoltaic power generation interconnected with the power system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.45-51
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• 2009

A low-voltage, low-power analog CMOS front-end for a cardiac pacemaker is proposed. The circuits include a 4th order switched-capacitor (SC) filter with a passband of 80-120 Hz and a SC variable gain amplifier whose control range is from 0 to 24-dB with 0.094 dB step. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption, and correlated double sampling technique is used for reducing the finite gain effect of an inverter. The proposed circuit has been designed in a $0.35-{\mu}m$ CMOS process, and it achieves 80-dB SFDR at 5-kHz sampling frequency. The power consumption is only 330 nW at 1-V power supply.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• Proceedings of the KIEE Conference
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• summer
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• pp.1214-1216
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• 2004

Conventional Switched Mode Power Supplies(SMPS) with diode-capacitor rectifier have distorted input current waveform with high harmonic contents. Typically, these SMPS have a power factor lower than 0,65. To improve with this problem the power factor correction(PFC) circuit of power supplies has to be introduced. PFC circuit have tendency to be applied in new power supply designs. The input active power factor correction circuits can be implemented using either the two-stage or the single-stage approach. In this paper, the comparative analysis of power factor correction circuit using feedforward control with average current mode single-stage flyback method converter and two-stage converter which is combination of boost and flyback converter. The two prototypes of 50W were designed and tested a laboratory experimental. Also, the comparative analysis is confirmed by simulation and experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.

• Journal of Power Electronics
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• v.7 no.3
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• pp.246-256
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• 2007

In this paper, a novel type auxiliary active edge resonant snubber assisted zero current soft switching pulse modulation Single-Ended Push Pull (SEPP) series load resonant inverter using IGBT power modules is proposed for cost effective consumer high-frequency induction heating (IH) appliances. Its operating principle in steady state is described by using each switching mode's equivalent operating circuits. The new multi resonant high-frequency inverter with series load resonance and edge resonance can regulate its high frequency output power under a condition of a constant frequency zero current soft switching (ZCS) commutation principle on the basis of the asymmetrical pulse width modulation (PWM) control scheme. Brand-new consumer IH products using the proposed ZCS-PWM series load resonant SEPP high-frequency inverter using IGBTs is evaluated and discussed as compared with conventional high-frequency inverters on the basis of experimental results. In order to extend ZCS operation ranges under a low power setting PWM as well as to improve efficiency, the high frequency pulse density modulation (PDM) strategy is demonstrated for high frequency multi-resonant inverters. Its practical effectiveness is substantially proved from an application point of view.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.26-30
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• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.1-7
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• 1999

A single RF transceiver evaluation board have been developed for the purpose of application to the 900MHz band transceiver contained RF-IC chip And environment test was evaluated. The RF-IC chipset includes LNA(Low Noise Amplifier), down-conversion mixer, AGC(Automatic Gain Controller), switched capacitor filter and down sampling mixer. The RF evaluation board for the testing of chipset contained various external matching circuits, filters such as RF/IF SAW(Surface Acoustic Wave) filter and duplexer and power supply circuits. With the range of 2.7~3.3V the operated chip revealed moderate power consumption of 42mA. The chip was well operated at the receiving frequency of 925~960MHz. Measurement result is similar to general RF receiving specification of the 900MHz digital mobile phone.