• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.226-231
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• 2010

This paper proposes a new coding technique for constructing error correcting high rate DC-free multimode code using a generator matrix generated from a sparse parity-check matrix. The scheme exploits high rate generator matrixes for producing distinct candidate codewords. The decoding complexity depends on whether the syndrome of the received codeword is zero or not. If the syndrome is zero, the decoding is simply performed by expurgating the redundant bits of the received codeword. Otherwise, the decoding is performed by a sum-product algorithm. The performance of the proposed scheme can achieve a reasonable DC-suppression and a low bit error rate.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.4
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• pp.569-574
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• 2017

In order to transmit information in a channel environment in which noise exists, a coding technique of information is required. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code(LDPC). LDPC and decoding characteristic features by Sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.498-504
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• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.771-774
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• 2010

In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1095-1102
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• 2016

In this paper, we propose a decoding scheme that can apply to a three dimensional turbo product code(TPC) with a single parity check code(SPC). In general, SPC is used an axis with shortest code length in order to maximize a code rate of the TPC. However, SPC does not have any error correcting capability, therefore, the error correcting capability of the three-dimensional TPC results in little improvement in comparison with the two-dimensional TPC. We propose two schemes to improve performance of three dimensional TPC decoder. One is $min^*$-sum algorithm that has advantages for low complexity implementation compared to Chase-Pyndiah algorithm. The other is a modified serial iterative decoding scheme for high performance. In addition, the simulation results for the proposed scheme are shown and compared with the conventional scheme. Finally, we introduce some practical considerations for hardware implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.758-763
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• 2008

We introduce a noise-predictive turbo equalization using noise filter in perpendicular magnetic recording(PMR) channel. The noise filter mitigates the colored noise in high-density PMR channel. In this paper, the channel detectors used are SOVA (Soft Output Viterbi Algorithm) and BCJR algorithm which proposed by Bahl et al., and the outer decoder used is LDPC (Low Density Parity Check) code that is implemented by sum-product algorithm. Two kinds of LDPC codes are experimented. One is the 0.5Kbyte (4336,4096) LDPC code with the code rate of 0.94, and the other is 1Kbyte (8432,8192) LDPC code with the code rate of 0.97.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.279-282
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• 2002

Here we introduce so called Reference code-weighted sum of all PN codes used in the system-. We do inner product operation between received PN code and Reference code rather than locally generated PN code in the receiver. Acquisition process can be accomplished by only one inner product during full period of PN code. It's essential innovation against present method which can be viewed successive hypothesis test by inner product for entire candidate PH codes set. Well -defined decision region makes it possible. We suggest the. criterion fur designing the decision region and find a condition for weight (coefficient) of Reference code.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.887-890
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• 2009

To transmit information over a channel in the presence of noise, there needs some technique to code the information. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code. LDPC and decoding characteristic features by sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.