• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.784-786
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• 2000

This paper implements and analyzes logically the Borrow Look-ahead Subtracter using Borrow Generator and Borrow Propagator. In subtracting calculation, we improve the calculating efficiency with using 4-bit subtracter which has Borrow Look-ahead Subtracters connection, and show that this is compatible with adder using the concept of Carry Generator and Carry Propagator. This subtracter may be useful in frequent subtracting calculation. We think this approach makes it possible to implement simple ALU(Arithmetic Logic Unit) with combining the concept of Borrow Look-ahead Subtracter and Carry Look-ahead Adder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.59-66
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• 2000

As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.836-845
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• 2001

A Novel fully-differential bipolar current subtracter(FCS) and its application to current controlled current amplifier(CCCA) for high-accuracy current-mode signal processing were designed. To obtain full-differential current output, the FCS was symmetrically composed of two current follower with low current-input impedance. The CCCA to control output current by the bias current was consisted of the subtracter and a current gain amplifier(CGA) with single-ended current output.. The simulation result shows that the FCS has current-input impedance of 5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100 $\mu$A to 20 mA. The power dissipation of the FCS and CCCA are 1.8 mW and 3 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.82-90
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• 2011

A novel class AB current subtracter(CS) and its application to Norton amplifier(NA) for low-power current-mode signal processing are designed. The CS is composed of a translinear cell, two current mirrors, and two common-emitter(CB) amplifiers. The principle of the current subtraction is that the difference of two input current applied translinear cell get from the current mirror, and then the current amplify through CB amplifier with ${\beta}$ times. The NA is consisted of the CS and wideband voltage buffer. The simulation results show that the CS has current input impedance of $20{\Omega}$, current gain of 50, and current input range of $i_{IN1}$ > $i_{IN2}{\geq}4I_B$. The NA has unit gain frequency of 312 MHz, transresistance of 130 dB, and power dissipation of 4mW at ${\pm}2.5V$ supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.1-6
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• 2008

There are many possible representations in denoting both positive and negative numbers in the binary number system to be applicable to the complexity of the hardware implementation, arithmetic speed, appropriate application, etc. Among many possibilities, the signed-magnitude representation, which keeps one sign bit and magnitude bits separately, is intuitively appealing for humans, conceptually simple, and easy to negate by flipping the sign bit. However, in the signed-magnitude representation, the actual arithmetic operation to be performed may require magnitude comparison and depend on not only the operation but also the signs of the operands, which is a major disadvantage. In a simple conceptual approach, addition/subtraction of two signed-magnitude numbers, requires comparator circuits, selective pre-complement circuits, and the adder circuits. In this paper circuits to obtain the difference of two numbers are designed without adopting explicit comparator circuits. Then by using the difference circuits, a universal signed-magnitude adder/subtracter is designed for the most general operation on two signed numbers.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.289-292
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• 2001

A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2087-2089
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• 2003

The presence of narrowband interference (NBI) in Direct-sequence code division multiple access (DS/CDMA) systems is an inevitable problem when the interference is strong enough. The improvement in the system performance employs by adaptive narrowband interference suppression techniques. Basically there have been two types of method for narrowband interference suppression estimator/subtracter approaches and transform domain approaches. In this paper the focus is on the type of estimator/subtracter approaches. However, the binary direct sequence (DS) signal, that acts as noise in the prediction process is highly non-Gaussian. The case of a Gaussian interferer with known in an autoregressive (AR) signal or a digital signal and also in a sinusoidal signal (Tone) that included in is paper. The proposed NBI suppression is presence in an adaptive IIR notch filter for lattice structure and more powerful by using a variable step-size algorithm. The simulation results show that the proposed algorithm can significantly increase the convergence rate and improved system performance when compare with adaptive least mean square algorithm (LMS).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.