Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a Low Power High Speed Conditional Select Adder/Subtracter for Next Generation ASIC Library

차세대 ASIC 라이브러리를 위한 고속 저전력 조건 선택 덧셈기/뺄셈기의 설계

  • 조기선 (東國大學校 半導體科學科) ;
  • 송민규 (東國大學校 半導體科學科)
  • Published : 2000.11.01
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Abstract

As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

본 논문에서는 DSP에서 필수적인 고속 저 전력 조건 선택 덧셈기/뺄셈기의 마크로 셀 라이브러리를 설계, 구축하였다. 덧셈기의 Carry전달 지연 시간을 최소로 하기 위한 CLA 기법과 연산 가능한 모든 결과 값을 미리 계산한 후 선택하는 조건 선택 기법을 적용하였다. 또한 이러한 설계방법이 8비트에서 64비트까지 자동 생성될 수 있도록 전용 프로그램을 작성하고 셀 기반 설계기법을 도입하여 Auto P&R Tool과 연계하여 자동으로 레이아웃이 가능하도록 하였다. 제안된 덧셈기/뺄셈기는 0.25${\mu}m$, 1-Poly, 5-Metal, N-well CMOS 공정을 사용하여 제작되었으며, 2.5V 단일 공급전압에서 지연시간, 소모 전력을 측정하였다. 측정결과 32 비트 덧셈기/뺄셈기의 경우 3.43ns의 지연시간과 42.8${\mu}w$/MHz의 전력소비를 나타내었다.

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References

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