• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.253-256
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• 2010

Different active layer thicknesses for zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric using injector type atomic layer deposition. The properties of the ZnO TFTs were influenced by the active thickness and width-to-length (W/L) ratio of the device. The threshold voltage of ZnO TFTs shifted positively as the active layer thickness decreased, while the subthreshold slope decreased. The W/L ratio of ZnO TFTs also affected the mobility and subthreshold slope. An optimized TFT structure exhibited an on-tooff current ratio of above 106 with solid saturation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.355-355
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• 2010

We studied the dependence of the performance of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) on the work function of source/drain metals. A strong impact of the various work functions and the light wavelengths on the transistor characteristics is found and explained using experimental data. We used an insulator of a high thickness (100nm) and back gate issues in SOI substrate, subthreshold swing was measured to 300~400[mV/dec] comparing with a ideal subthreshold swing of 60[mV/dec]. Excellent characteristics of Al/Si was demonstrated higher on/off current ratios of ${\sim}10^7$ than others. In addition, extensive photoresponse analysis has been performed using halogen and deuterium light sources(200<$\lambda$<2000nm).

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.221-226
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• 2008

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.450-453
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• 1999

In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.225-230
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• 1994

In this paper, we have fabricated short channel MOSFETs with these parameters to verify the validity of process parameters extraction by DTC method. The experimental results of fabricated short channel devices according to the optimal process parameters demonstrate good device characteristics such as good drain current-voltage characteristics, low body effects and threshold voltage of$\leq$+-.1.0V, high punch through and breakdown voltage of$\leq$12V, low subthreshold swing(S.S) values of$\leq$105mV/decade.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1990년도 추계학술대회 논문집
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• pp.55-59
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10$\mu\textrm{m}$) were fabricated using RTP(Rapid Thermal Processor) and hydrogen passivation. The N+ Source, drain and gate were annealed and recrystallized using RTP at temperature of 1000$^{\circ}C$-1100$^{\circ}C$. But the active areas were now specially crystallized before growing the gate oxide. Without the hydrogen passivation, excellent transistor characteristics (ON/OFF=5${\times}$10$\^$6/, s=85mv/dec, I$\_$L/=51pA/$\mu\textrm{m}$) were obtained for 1.5$\mu\textrm{m}$ MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 춘계학술대회
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• pp.560-561
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• 2022

본 논문은 Nanosheet FET(NSFET)와 FinFET의 소자 성능을 3차원 소자 시뮬레이션을 통하여 다양한 구조의 NSFET와 FinFET의 소자 시뮬레이션을 한다. NSFET와 FinFET의 전류-전압 특성을 시뮬레이션하였고, 그 전류-전압 특성으로부터 추출한 문턱전압, 문턱전압이하 기울기 등의 성능을 비교하였다. NSFET이 FinFET보다 전류-전압 특성에서 드레인 전류가 더 많이 흐르며 더 높은 문턱전압을 갖는다. 문턱전압이하 기울기는 NSFET와이 FinFET보다 더 가파른 기울기를 갖는다.