• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.9
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• pp.4023-4043
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• 2016

Network virtualization has been regarded as a core attribute of the Future Internet. In a network virtualization environment (NVE), multiple heterogeneous virtual networks can coexist on a shared substrate network. Thus, a substrate network failure may affect multiple virtual networks. In this case, it is increasingly critical to provide survivability for the virtual networks against the substrate network failures. Previous research focused on mechanisms that ensure the resilience of the virtual network. However, the resource efficiency is still important to make the mapping scheme practical. In this paper, we study the survivable virtual network embedding mechanisms against substrate link and node failure from the perspective of improving the resource efficiency. For substrate link survivability, we propose a load-balancing and re-configuration strategy to improve the acceptance ratio and bandwidth utilization ratio. For substrate node survivability, we develop a minimum cost heuristic based on a divided network model and a backup resource cost model, which can both satisfy the location constraints of virtual node and increase the sharing degree of the backup resources. Simulations are conducted to evaluate the performance of the solutions. The proposed load balancing and re-configuration strategy for substrate link survivability outperforms other approaches in terms of acceptance ratio and bandwidth utilization ratio. And the proposed minimum cost heuristic for substrate node survivability gets a good performance in term of acceptance ratio.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.14-16
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• 2009

Surface driven switching of the liquid crystal bulk arising from the coupling between an applied electric field and a polarized state of a nematic liquid crystal, both localized at the substrate surface, is reported. Fast switching is demonstrated in a hybrid aligned nematic cell with a fringe electric field generated by comb-like electrode structure.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.1
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• pp.145-164
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• 2014

Network virtualization provides a promising tool to allow multiple heterogeneous virtual networks to run on a shared substrate network simultaneously. A long-standing challenge in network virtualization is the Virtual Network Embedding (VNE) problem: how to embed virtual networks onto specific physical nodes and links in the substrate network effectively. Recent research presents several heuristic algorithms that only consider single topological attribute of networks, which may lead to decreased utilization of resources. In this paper, we introduce six complementary characteristics that reflect different topological attributes, and propose three topology-aware VNE algorithms by leveraging the respective advantages of different characteristics. In addition, a new KS-core decomposition algorithm based on two characteristics is devised to better disentangle the hierarchical topological structure of virtual networks. Due to the overall consideration of topological attributes of substrate and virtual networks by using multiple characteristics, our study better coordinates node and link embedding. Extensive simulations demonstrate that our proposed algorithms improve the long-term average revenue, acceptance ratio, and revenue/cost ratio compared to previous algorithms.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.822-825
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• 2006

We propose a transflective In-Plane Switching mode in which patterned retarder is placed only on the reflective area of the upper substrate side. By selecting optic axes of Half Wavelength Plate and Liquid Crystal as 24 and 90 degree with respect to polarizer, condition of low reflectance for visible wavelength range at black state is found.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1511_1512
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• 2009

This paper presents a polarization switching antenna integrated with silicon RF MEMS SPDT switches in the form of a package. A low-loss quartz substrate made of SoQ (silicon-on-quartz) bonding is used as a dielectric material of the patch antenna, as well as a packaging lid substrate of RF MEMS switches. The packaging/antenna substrate is bonded with the bottom substrate including feeding lines and RF MEMS switches by BCB adhesive bonding, and RF energy is transmitted from signal lines to antenna by slot coupling. Through this approach, fabrication complexity and degradation of RF performances of the antenna due to the parasitic effects, which are all caused from the packaging methods, can be reduced. This structure is expected to be used as a platform for reconfigurable antennas with RF MEMS tunable components. A linear polarization switching antenna operating at 19 GHz is manufactured based on the proposed method, and the fabrication process is carefully described. The s-parameters of the fabricated antenna at each state are measured to evaluate the antenna performance.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.407-410
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• 1987

A layout design concept which suppress the substrate current generated during the switching transients of an CMOS inverter is presented. The amount of hot carriers and the peak value of substrate current can be reduced by changing the device geometry ratio of driver and load device of an CMOS inverter.

• Journal of IKEEE
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• v.17 no.3
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• pp.229-233
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• 2013

We investigated electrical conduction and resistance switching behavior of the Ag/ZnO/Ti structures for random access memory devices. These films were prepared on glass substrate by dc sputtering technique at room temperature. The resistance switching follows unipolar switching mode with small switching voltages (0.4 V - 0.6 V). Two electrical conduction mechanisms dominating the LRS and HRS are Ohmic and trap-controlled space charge limited current, respectively. These both conductions are consistent with the filamentary model. Based on the filamentary model, the switching mechanism was also interpreted.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.33-36
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• 1999

In this paper, we proposed a simultaneous switching noise(SSN) reduction technique in muti-layer beards(MLB) for high-speed digital applications and analyzed them using the Finite Difference Time Domain(FDTD) method. The new method by conductive dielectric substrates reduces SSN couplings and resonances, significantly, which cause series malfunctions in the modem high-speed digital applications.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology