• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.925-926
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• 2006

In the multi-agent system for a single task, the action selection can be made for the real-time environment by using the global coordination space, global coordination graph and MAX-PLUS algorithm. However, there are some difficulties in multi-agent system for multi-tasking. In this paper, a real-time decision making method is suggested by using coordination space, coordination graph and dynamic coordinated state of multi-agent system including many agents and multiple tasks. Specifically, we propose locally dynamic coordinated state to effectively use MAX-PLUS algorithm for multiple tasks completion. Our technique is shown to be valid in the box pushing simulation of a multi-agent system.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1188-1195
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• 2014

This paper presents an analytical technique for reliability evaluation of electrical distribution network (EDN) containing distributed generation (DG). Based on hierarchical levels of circuit breaker controlling zones and feeder sections, a directed-relation-graph (DRG) for an END is formed to describe the hierarchical structure of the EDN. The reliability indices of EDN and load points can be evaluated directly using the formed DRG, and the reliability evaluation of an EDN containing DGs can also be done without re-forming the DRG. The proposed technique incorporates multi-state models of photovoltaic and diesel generations, as well as weather factors. The IEEE-RBTS Bus 6 EDN is used to validate the proposed technique; and a practical campus EDN containing DG was also analyzed using the proposed technique.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.628-634
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• 1995

In the area of assembly process of micro-chips and electronic parts on the printed circuit board, surface mounting device(SMD) is used as a fundamental tool. Generally speaking, the motion of the SMD is based on the ball screw system operated by any type of actuators. The ball screw system is a mechanical transformer which converts the mechanical rotational motion to the translational one. Also, this system could be considered as an efficient motion device against mechanical backash and friction. Therefore a dynamic modeling and stste sensitivity analysis of the ball screw system in SMD have to be done in the initial design stage. In this paper, a simple mathematical dynamic model for this system and the sensitivity snalysis are mentioned. Especially, the bond graph approach is used for graphical modeling of the dynamic system before analysis stage. And the direct differentiation method is used for the state sensitivity analysis of the system. Finally, some trends for the state variables with respect to the design variables could be suggested for the better design based on the results on the results of dynamic and state sensitivity.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.521-524
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• 1988

This paper describes BSDL(Behavioral/Structural Description Language), CDTF(Control Data Text File) and state synthesizer built for use in ICSC(InCheon Silicon Compiler). BSDL describes structral and behaviral specifications of an ASIC(Application Specific IC) for digital system design. ICSC's paser generates CDTF consists of if-then-else, arithmetic and data transfer statement according to each BSDL statement. State synthesizer generates CCG(Control Constraint Graph) in consideration of execution of statement and generates VCG (Variable Constraint Graph) in consideration use of variable generation and use of variable. Also, it involves allocating algorithm operation nodes in the data path and the control path to machine states with minimum state number and as small area as possible.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.3
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• pp.27-37
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• 2021

Highly informative heuristics in AI planning can help to a more efficient search a solutions. However, in general, to obtain informative heuristics from planning problem specifications requires a lot of computational effort. To address this problem, we propose a Partial Planning Graph(PPG) and Mixed Heuristics for solving planning problems more efficiently. The PPG is an improved graph to be applied to can find a partial heuristic value for each goal condition from the relaxed planning graph which is a means to get heuristics to solve planning problems. Mixed Heuristics using PPG requires size of each graph is relatively small and less computational effort as a partial plan generated for each goal condition compared to the existing planning graph. Mixed Heuristics using PPG can find partial interactions for each goal conditions in an effective way, then consider them in order to estimate the goal state heuristics. Therefore Mixed Heuristics can not only find interactions for each goal conditions more less computational effort, but also have high accuracy of heuristics than the existing max and additive heuristics. In this paper, we present the PPG and the algorithm for computing Mixed Heuristics, and then explain analysis to accuracy and the efficiency of the Mixed Heuristics.

• Journal of the Society of Naval Architects of Korea
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• v.59 no.6
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• pp.393-399
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• 2022

During the ship hull design process, resistance performance estimation is generally calculated by simulation using computational fluid dynamics. Since such hull resistance performance simulation requires a lot of time and computation resources, the time taken for simulation is reduced by CPU clusters having more than tens of cores in order to complete the hull design within the required deadline of the ship owner. In this paper, we propose a method for estimating resistance performance of ship hull by simulation using a graph neural network. This method converts the 3D geometric information of the hull mesh and the physical quantity of the surface into a mathematical graph, and is implemented as a deep learning model that predicts the future simulation state from the input state. The method proposed in the resistance performance experiment of simple hull showed an average error of about 3.5 % throughout the simulation.

• Journal of the Korean Mathematical Society
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• v.59 no.4
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• pp.757-774
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• 2022

Let a and b be positive even integers. An even [a, b]-factor of a graph G is a spanning subgraph H such that for every vertex v ∈ V (G), d_H(v) is even and a ≤ dH(v) ≤ b. Let κ(G) be the minimum size of a vertex set S such that G - S is disconnected or one vertex, and let σ₂(G) = min_uv∉E(G) (d(u)+d(v)). In 2005, Matsuda proved an Ore-type condition for an n-vertex graph satisfying certain properties to guarantee the existence of an even [2, b]-factor. In this paper, we prove that for an even positive integer b with b ≥ 6, if G is an n-vertex graph such that n ≥ b + 5, κ(G) ≥ 4, and σ₂(G) ≥ ${\frac{8n}{b+4}}$, then G contains an even [4, b]-factor; each condition on n, κ(G), and σ₂(G) is sharp.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.4
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• pp.66-75
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• 1998

In many case of optimal design and sensitivity analysis, obtaining of transfer function between input and output variables is a difficult and time-consuming problem. The bond graph modeling is a method that is used for making it easy to analyze complex systems composed of mechanical and electrical parts. It gives us a simple and systematic tool to get state-space equations easily. And we can obtain the transfer function graphically using bond graph and Mason's rule. This paper shows how bond graphs are converted to block diagram and how Mason's rule is applied. And the simple direct method to obtain transfer function from bond graph is introduced. As a example, induction of transfer function of electric power steering composed of mechanical and electrical parts will be done.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11B
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• pp.1020-1029
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• 2008

This paper proposes an high speed pattern matching algorithm and its implementation. The pattern matcher is used to check patterns from realtime input packet. The proposed algorithm can find exact string, range of string values, and combination of string values from input packet at high speed. Given string and rule set are modelled as a state transition graph which can find overlapped strings simultaneously, and the state transition graph is partitioned according to input implicants to reduce implementation complexity. The pattern matcher scheme uses the transformed state transition graph and input packet as an input. The pattern matcher was modelled and implemented in VHDL language. Experimental results show the proprieties of the proposed approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.47-54
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• 2005

In this paper, a new synthesis method for testability of synchronous sequential circuits is suggested on an incompletely-specified state transition graph (STG) by reducing the number of redundant faults. In the suggested synthesis method, 1) a given STG is modified by adding undefined states and unspecified input transitions using distinguishable transition, 2) the STG is modified to be strongly-connected as much as possible. Experimental results with MCNC benchmark show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, and much higher fault coverage is obtained.