• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.64-67
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• 2018

A new CMOS neuron circuit for implementing bistable synapses with spike-timing-dependent plasticity (STDP) properties has been proposed. In neuromorphic systems using STDP properties, the short-term dynamics of the synaptic efficacies are governed by the relative timing of the pre- and post-synaptic spikes, and the efficacies tend asymptotically to either a potentiated state or to a depressed one on long time scales. The proposed circuit consists of a negative shifter, a current starved inverter and a schmitt trigger designed using 0.18um CMOS technology. The simulation result shows that the proposed circuit can reduce the total size of neurons, and the spike energy of the proposed circuit is much less compared to the conventional circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.657-663
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• 2016

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.210-215
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• 2017

We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• Journal of IKEEE
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• v.26 no.4
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• pp.633-638
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• 2022

Rencently, neuromorphic systems of spiking neural networks (SNNs) that imitate the human brain have attracted attention. Neuromorphic technology has the advantage of high speed and low power consumption in cognitive applications and processing. Resistive random-access memory (RRAM) for SNNs are the most efficient structure for parallel calculation and perform the gradual switching operation of spike-timing-dependent plasticity (STDP). RRAM as synaptic device operation has low-power processing and expresses various memory states. However, the integration of RRAM device causes high switching voltage and current, resulting in high power consumption. To reduce the operation voltage of the RRAM, it is important to develop new materials of the switching layer and metal electrode. This study suggested a optimized new structure that is the Metal/Al₂O₃/HfO_x/SWCNTs/N+silicon (MOCS) with single-walled carbon nanotubes (SWCNTs), which have excellent electrical and mechanical properties in order to lower the switching voltage. Therefore, we show an improvement in the gradual switching behavior and low-power I/V curve of SWCNTs-based memristors.