• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.194-200
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• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

• Journal of Information Display
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• v.10 no.3
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• pp.101-106
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• 2009

In this study, a physical OLED analog behavior model for SPICE simulation was described using the Verilog-A language. The model was presented through theoretical equations for the J-V characteristics of OLED derived according to the internalcarrier emission equation based on a diffusion model at the Schottky barrier contact, and the mobility equation based on the Pool-Frenkel model. The accuracy of this model was examined by comparing it with the results of the device simulation that was conducted.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.54-61
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• 1999

We suggested a macro medel for MOS transistors, which incorporates the distributed substrate resistance by using a method which utilizes external diodes on SPICE MOS model. By fitting the simulated s-parameters to the measures ones, we obtained a model set for the W=200TEX>$\mu\textrm{m}$ and L=0.8TEX>$\mu\textrm{m}$ NMOS transistor, and also analyzed the effects of distributed substrate resistance in the RF range. By comparing the physical parameters calculated from simulated s-parameters such as ac resistances and capacitances with the measured ones, we confirmed the validity of the simulation results. For the frequencies below 10GHz, it seems appropriated to use a simple macro model which utilizes the existing SPICE MOS model with junction diodes, after including one lumped resistor each for gate and substrate nodes.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.39-47
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• 1994

The drain current reduction effect due to the side-gating phenomena resulted from interaction between the neighbor gates is lead to degradation of circuit performance. In this paper, these effect were modelized for circuit simulation with the shift of threshold voltage resulting from negative charge formation and the analysis of substrate leakage current resulting trapping effect. To remove dificiencies of the conventional three terminal structure, these model were implemented in SPICE with the four terminal structure, and then the constructed environment enables the simulation of circuit performance degradation resulted from side-gating effect. The validity of implemented model is proved by comparisoin with experiment data.

• ETRI Journal
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• v.34 no.4
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.24-29
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• 2009

In order to model the high temperature dependence of the cutoff frequency $f_T$ in $0.18{\mu}m$ deep n-well isolated bulk NMOSFET, high temperature data of electron velocity of bulk MOSFETs from $30^{\circ}C$ to $250^{\circ}C$ are obtained by an accurate RF extraction method using measured S-parameters. From these data, an improved temperature-dependent electron velocity equation is developed and implemented in a BSIM3v3 SPICE model to eliminate modeling error of a conventional one in the high temperature range. Better agreement with measured $f_T$ data from $30^{\circ}C$ to $250^{\circ}C$ are achieved by using the SPICE model with the improved equation rather than the conventional one, verifying its accuracy of the improved one.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.59-63
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• 2005

A simulation method combined with the simulation program with integrated circuit emphasis (SPICE) and the technology computer-aided design (TCAD) has been proposed to estimate the electrical characteristics of the metal-ferroelectric-semiconductor field effect transistor (MFS/MFISFET). The complex behavior of the ferroelectric property was analyzed and surface potential of the channel region in the MFS gate structure was calculated with the numerical TCAD method. Since the calculated surface potential is equivalent with the surface potential obtained with the SPICE model of the conventional MOSFET, we can obtain the current-voltage characteristics of MFS/MFISFET corresponding to the applied gate bias. Therefore, the proposed method will be very useful for the design of the integrated circuits with MFS/MFISFET memory cell devices.

• Journal of the Korea Safety Management & Science
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• v.7 no.4
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• pp.141-163
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• 2005

The international SPICE (Software Process Improvement and Capability determination) Project ISO/IEC 15504(SPICE : Software Process Improvement and Capability determination) is an emerging International Standard on SPA(Software Process Assessment). A prime motivation for developing this standard has been the perceived need for an internationally recognized software process assessment framework that pulls together the existing public and proprietary models and methods. A SPICE assessment can be considered as one of representative SPA model since assessors assign ratings to indicators and metrics to measure the capability of software process. But this models doesn't provide a systematic measurement procedures and dynamic method for SPI(Software Process Improvement). Through the evaluation of SPICE is capable of providing a substantiated basis for using the notion of capability, as well as providing information for nacessary improvements to the standard using 6sigma process. As a result, this paper propose a measurement procedure and guidelines for application of 6sigma process to guarantee the reliability in SPI and suggest the structure to support SPI on overall organization.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.431-434
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• 2008

The physical OLED analog behavioral model for SPICE simulation has been described using Verilog-A language. The model is based on the carrier-balance between the hole and electron injected through Schottky barrier at anode and cathode. The accuracy of this model was examined by comparing with the results from device simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.