• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.1-12
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• 2021

3D printing, which designs product in three dimensions, draws attention as a technology that will lead the future for it dramatically shortens time for production without assembly, no matter how complex the structure is. The paper studies the latest researches of 3D-printed electronics and introduces papers studied electronics components, power supply, circuit interconnection and 3D-printed PCBs' applications. 3D-printed electronics showed possibility to simplify facilities and personalize electric devices by providing one-stop printing process of electronic components, soldering, stacking, and even encapsulation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.55-61
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• 2022

In this study, properties of Pb-free solder joints which were combined using Sn-3.0Ag-0.5Cu (SAC305) Pb-free solder with a mid-temperature type of melting temperature and Sn-57Bi-1Ag Pb-free solder with a low-temperature type of melting temperature were reported. Combined Pb-free solder joints were formed by reflow soldering processes with ball grid array (BGA) packages which have SAC305 solder balls and flame retardant-4 (FR-4) printed circuit boards (PCBs) which printed Sn-57Bi-1Ag solder paste. The reflow soldering processes were performed with two types of temperature profiles and interfacial properties of combined Pb-free solder joints such as interfacial reactions, formations of intermetallic compounds (IMCs), diffusion mechanisms of Bi, and so on were analyzed with the reflow process conditions. In order to compare reliability characteristics of combined Pb-free solder joints, we also conducted thermal shock test and analyzed changes of mechanical properties for joints from a shear test during the thermal shock test.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.1-7
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• 2020

The backside metallization process is typically used to attach a chip to a lead frame for semiconductor packaging because it has excellent bond-line and good electrical and thermal conduction. In particular, the backside metal with the Ag/Sn/Ag sandwich structure has a low-temperature bonding process and high remelting temperature because the interfacial structure composed of intermetallic compounds with higher melting temperatures than pure metal layers after die attach process. Here, we introduce a die attach process with the Ag/Sn/Ag sandwich structure to apply commercial semiconductor packages. After the die attachment, we investigated the evolution of the interfacial structures and evaluated the shear strength of the Ag/Sn/Ag sandwich structure and compared to those of a commercial backside metal (Au-12Ge).

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.1
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• pp.22-31
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• 2008

The operating window method is a novel approach in quality improvement. But it has not received deserved attention in academic research. If a critical factor for competing failure modes can be identified, the probability of failure can be reduced by widening the operating window of this factor. Traditional SN ratio for the operating window advocated by Taguchi has a critical shortcoming, which has been derived under the assumption that failure rates are determined by the operating window factor only. A new metric for robustness is given for the operating window method, which has relaxed the restrictive assumption of Taguchi's SN ratio. And procedures for determining optimal conditions based on the new metric is presented. The effectiveness of the proposed approach over the traditional practice is tested with the aid of a wave soldering process.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.92-99
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• 2021

The ever-growing demand for enhanced competitiveness of engineered systems require designing in quality strategies that can efficiently incorporate multiple design attributes into a system. In a robust design, there must be consideration for any uncontrollable factors that should not be disregarded in the design process. Studies on multi-attribute design challenges usually assume mutual utility independence amongst the design attributes. However, mutual utility independence does not exist in every design situation. In this study, a new robust design methodology that has two utility-dependent attributes are presented. The proposed method was then compared with a traditional robust design that utilizes a wave soldering process design. The results of this case study indicate that the proposed method yields a better solution than the traditional method.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.13-19
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• 2018

The soldering property of Pb-containing solder(Sn-Pb) and Pb-free solders(Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.7Cu-1.6Bi-0.2In) for solar combiner box module was compared. The solar combiner box module was composed of voltage and current detecting modules, diode modules, and other modules. In this study, solder paste printability, printing shape inspection, solder joint property, X-ray inspection, and shear force measurements were conducted. For optimization of Pb-free soldering process, step 1 and 2 were divided. In the step 1 process, the printability of Pb-containing and Pb-free solder alloys were estimated by using printing inspector. Then, the relationship between void percentages and shear force has been estimated. Overall, the property of Pb-containing solder was better than two Pb-free solders. In the step 2 process, the property of reflow soldering for the Pb-free solders was evaluated with different reflow peak temperatures. As the peak temperature of the reflow process gradually increased, the void percentage decreased by 2 to 4%, but the shear force did not significantly depend on the reflow peak temperature by a deviation of about 0.5 kgf. Among different surface finishes on PCB, ENIG surface finish was better than OSP and Pb-free solder surface finishes in terms of shear force. In the thermal shock reliability test of the solar combiner box module with a Pb-free solder and OSP surface finish, the change rate of electrical property of the module was almost unchanged within a 0.3% range and the module had a relatively good electrical property after 500 thermal shock cycles.

• Journal of the Korean Solar Energy Society
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• v.37 no.2
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• pp.77-85
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• 2017

Thin crystalline silicon (C-Si) solar cell is expected to be a low price energy source by decreasing the consumption of Si. However, thin c-Si solar cell entails the bowing and crack issues in high temperature manufacturing process. Thus, the conventional tabbing process, based on high temperature soldering (> $250^{\circ}C$), has difficulties for applying to thin c-Si solar cell modules. In this paper, a conductive paste (CP) based interconnection process has been proposed to fabricate thin c-Si solar cell modules with high production yield, instead of existing soldering materials. To optimize the process condition for CP based interconnection, we compared the performance and stability of modules fabricated under various lamination temperature (120, 150, and $175^{\circ}C$). The power from CP based module is similar to that with conventional tabbing process, as modules are fabricated. However, the output of CP based module laminated at $120^{\circ}C$ decreases significantly (14.1% for Damp heat and 6.1% for thermal cycle) in harsh condition, while the output drops only in 3% in the samples process at $150^{\circ}C$, $175^{\circ}C$. The peel test indicates that the unstable performance of sample laminated at $120^{\circ}C$ is attributed to weak adhesion strength (1.7 N) between cell and ribbon compared to other cases (2.7 N). As a result, optimized lamination temperature for CP based module process is $150^{\circ}C$, considering stability and energy consumption during the fabrication.

• Korean Journal of Materials Research
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• v.15 no.8
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• pp.528-535
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• 2005

It is inclined to increase that use of hazardous substances such as lead(Pb), mercury (Hg), cadmium(Cd) etc. are prohibited in the electronics according to environmental friendly policies of an advanced nation for protecting environment of earth. As this reasons, many researches for ensuring the reliability were proceeding in Pb free soldering process. n the flux remains on the PCB(printed circuit board) in the soldering process or the electronics exposed to corrosive environment, it becomes the reasons of breakdown or malfunction of the electronics caused by corrosion. Therefore in this studies we researched the polarization and Tafel properties of Sn40Pb and SnCu system solders based on the electrochemical theory. The experimental polarization curves were measured in distilled ionized water and 1 mole $3.5 wt\%$ NaCl electrolyte of $40^{\circ}C$, pH 7.5. Ag/AgCl and graphite were utilized by reference and counter electrodes, respectively. To observe the electrochemical reaction, polarization test was conducted from -250mV to +250mV. From the polarization curves composed of anodic and cathodic curves, we obtained Tafel slop, reversible electrode potential(Ecorr) and exchange current density((cow). In these results, we compared the corrosion rate of SnPb and SnCu solders.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.218-221
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• 2007

The surface mounting technology of 0402 electric chip part is necessary to fabricate a high density and multi-functional module, but there is a limitation of the technology, like as a bridge and self-alignement. This work estimated SMT processing factors of 0402 chip. To obtain optimum SMT process, we evaluated effects of stencil thickness, shape of hole on printability and mountability. Printability shows best results under the thickness of $80{mu}m$ with circle hole shape and 90% square hole shape. In case of chip mounting process, chip mis-alignment and bridge was occurred rarely in same conditions. In more thin stencil thickness, $50{mu}m$, strength of 1005 chip parts was poor, because of amount of printed solder was insufficient.