• International Journal of Contents
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• 제7권3호
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• pp.19-28
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• 2011

This paper presents a fast and practical motion synthesis algorithm for massive number of quadruped animals. The algorithm constructs so called speed maps that contain a set of same style motions but different speed from a single cyclic motion by using IK(Inverse Kinematics) solver. Then, those speed maps are connected each other to form a motion graph. At run time, given a point trajectory that obtained from user specification or simulators, the algorithm retrieves proper speed motions from the graph, and modifies and stitches them together to create a long seamless motion in real time. Since our algorithm mainly targets on the massive quadruped animal motions, the motion graph create wide variety of different size of characters for each trajectory and automatically adjusted synthesized motions without causing artifact such as foot skating. The performance of algorithm is verified through several experiments

• Proceedings of the Korean Society of Medical Physics Conference
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• 한국의학물리학회 2002년도 Proceedings
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• pp.311-313
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• 2002

We are under development of a 3D PET scanner with depth of interaction (DOI) capable of high sensitivity and high resolution. In this scanner, a maximum data transfer rate of coincidence pair's event information is 10 Mcps and one event is a 64-bit data format. This maximum data transfer rate corresponds by 10 times a conventional PET scanner. A data acquisition system, which fulfills the specification of this scanner, is considered for parallel collection with banks including several coincidence units. Data transfer rate is improved by optimizing parameters of a message size, and so on.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.69-72
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• 2000

This paper describes an SRAM write driver circuit which dissipates small power. The write driver utilizes a dual sized transistor structure to reduce operating current in the write cycle. In the case of higher voltage comparing to Vcc, only one transistor is active, while in the case of low Vcc two transistors are active so as to deliver the current twice. Thus though with the high voltage operation, the power consumption is reduced with keeping the speed in a given specification. Simulation results have verified the functionality of the new circuit and write power is reduced by 7 % per bit.

• Proceedings of the KIEE Conference
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.165-167
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• 2006

In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 KHz (0.3 MIPS) while consuming only about few pJ/instruction.

• Journal of Mechanical Science and Technology
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• 제19권spc1호
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• pp.473-480
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• 2005

A three axes marine satellite antenna has been developed. As a design step, a CAD model for the antenna has been created according to the design requirements. Kinematic analyses are carried out to insure design specification and to check collision detection of the CAD model. Marine satellite antennas experience base motions, and a relevant control system should control the three antenna axis to point to the satellites accurately. A sensor fusion algorithm and a PIDA (Proportional, Integral, Derivative, Acceleration) control algorithm are designed and implemented to control the yaw, level, and cross-level angle of a small size satellite marine antenna. Antenna stabilization control experiments are performed using a test simulator which gives the antenna base motions. Experimental results show small pointing errors, which is less than 0.2 degree for the level, cross-level, and yaw axis.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제57권9호
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• pp.1660-1668
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• 2008

The WiBro was adopted to the 3G international standard. By the change of specification from Wave 1 to Wave 2, MIMO technology is applied in order to increase the speed of downlink. By MIMO the RF part of WiBro base station is increased to 2 Tx paths. Therefore, the size of RF part is bigger and material cost is increased. For reducing these demerits, the RF part which is consisted of PA, LNA, and TDD switch is designed to one complex RF unit. Also, the experimental results of the RF unit have been discussed. Since the complex RF unit is more compact than the RF part of Wave 1 base station, it can be used as the RF part of Wave 2 base station with 2T/2R MIMO.

• Journal of Korean Society for Quality Management
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• 제30권2호
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• pp.99-117
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• 2002

Variable sampling interval(VSI) and variable sample size(VSS) control charts vary the sampling rate for the next sample depending on the current chart statistic. This paper develops EWMA charts with the VSI and VSS features, and investigates the effectiveness of these charts in context of an economic model. The economic properties of these charts are evaluated by using Markov chain methods. The model contains cost parameters which allow the specification of the costs associated with sampling, false alarms, and operating off target. This economic model can be used to quantify the cost saving that can be obtained by using control charts with the VSI and VSS features instead of with the fixed sampling rate(FSR) feature, and can also be used to gain insight into the way that control charts with the VSI and VSS features should be designed to achieve optimal economic performance. The economic performance of X charts with the VSI and VSS features is also considered.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 한국소성가공학회 1998년도 금형가공 심포지엄
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• pp.28-42
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• 1998

Spinning is one of the incremental forming process by the rotating mandrel and forming roller, and has been applied to manufacturing the wheel disc of automobile to simplify the manufacturing process and to improve the mechanical properties of product. In the proesent study the process variables have been extracted and considered to decide the specification of the spinning machine. The maximum values of working load and power have been evaluated and the blank size has been disigned. The shape and dimensionof forming roller have been designed and the process condition such a s rotational velocity of mandrel and the feedrate of roller have been decided.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권4호
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• pp.452-474
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• 2010

Formidable growth of Internet technologies has revealed challenging issues about its scale and performance evaluation. Modeling and simulation play a central role in the evaluation of the behavior and performance of the large-scale network systems. Large numbers of nodes affect simulation performance, simulation execution time and scalability in a weighty manner. Most of the existing simulators have numerous problems such as size, lack of system theoretic approach and complexity of modeled network. In this work, a scalable discrete-event modeling approach is described for studying networks' scalability and performance traits. Key fundamental attributes of Internet and its protocols are incorporated into a set of simulation models developed using the Discrete Event System Specification (DEVS) approach. Large-scale network models are simulated and evaluated to show the benefits of the developed network models and approaches.