• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 추계학술대회논문집B
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• pp.556-561
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• 2000

Comprehensive numerical computations are made of side-heated squire cavity which is exposed to time dependent external mechanical forcing. Numerical solutions are acquires to the governing two-dimensional Navier-Stokes equations for a Boussinesq fluid. Time dependent heat transfer characteristics of interior fluid are analyzed to illustrate resonance phenomenon. When system is exposed to pure sinusoidal mechanical forcing, the numerical results disclose that the basic mechanism of resonance of mechanical forcing is same as that of thermal forcing of Ref. [3, 9]. In comparatively small amplitude of mechanical forcing, thermal characteristics of the system are similar to basic system(${\varepsilon}=0$).

• 대한기계학회논문집
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• 제18권2호
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• pp.380-388
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• 1994

Study on the chaotic stirring has been performed numerically and experimentally for a shallow rectangular tank accompanying a vortex shedding. The model is composed of a rectangular tank with a vertical plate with a length half the width of the tank. The tank is subject to a horizontal sinusoidal oscillation. The chaotic stirring was analysed by Poincare sections, unstable manifolds and Lyapunov exponents. As Reynolds number is increased the stirring effect is decreased due to the growth of a regular regions near the lower surface of the tank. In the other hand decrease of Reynolds number gives a weaker vortex shedding resulting in the poorer stirring effect. It was also found that the Lyapunov exponent is the highest at the dimensionless period of 1.3-1.5, which seems to be the best condition for the efficient stirring. The experimental visualization for the deformation of materials exhibits the striation pattern similar to the unstable manifold obtained numerically.

• 한국통신학회논문지
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• 제12권5호
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• pp.527-534
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• 1987

진동에 관한 비선형 1계연립미분방정식을 아나로그 시뮬레이션으로 2상전압제어발진을 시켜 유용성을 확인하였다. 2상신호를 각각 제곱하여 합성하는 부분과 곱셈부분의 실제회로 구성시 복잡하고 가격이 높아지므로 정류 회로와 스위칭회로로 대치하여 회로의 단순화와 가격 저렴화를 이루었다. 본 논문에서 제시된 회로는 제어 압력전압에 주파수가 정확한 비례관계를 가졌고, 응답 속도가 비교적 빠르고 또한 위상오차가 매우 적었으며 주파수비가 10:1 이상에서도 저왜율과 정진폭으로 동작하였다.

• 산업기술연구
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• 제11권
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• pp.43-53
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• 1991

Two kinds of simple active oscillators are proposed and analyzed assuming that operational amplifier has two-poles frequency characteristics. The first circuit is composed of one operational amplifier, one resistor and one grounded capacitor. The second oscillator is realized with one operational amplifier and three resitors. Proposed oscillators have the low sensitivity of the oscillation frequency for little variations of the passive element values. By the experimental results obtained with Op-Amp. ${\mu}A741$, the simple oscillators can be useful for the frequency range $1.25 KHz{\leq}f_{01}{\leq}40KHz$ for the active-RC type or $45.45 KHz{\leq}f_{02}{\leq}400KHz$ for the active-R oscillator, and it is shown to transform the active-R oscillator circuit into the voltage controlled type. Therefore, two kinds of oscillator circuit are attractive for the IC realization, because they have one operational amplifier, one resistor and one grounded capacitor, or three resistors.

• 대한전자공학회논문지SD
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• 제40권4호
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• pp.65-73
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• 2003

본 논문은 진동형 각속도 검출 센서로부터 각속도 신호를 검출하는 애널로그 신호처리 ASIC의 구현에 관한 것이다. 각속도 검출 센서의 출력은 구조적으로 콘덴서의 용량변화로 나타나므로 이를 검출하기 위하여 전하 증폭기를 이용하였으며, 센서의 구동에 필요한 자체발진회로는 각속도 검출 센서의 공진 특성을 이용한 정현파 발진회로로 구현하였다. 특히 센서의 제조 공정으로 인한 특성 변화나 온도 변화와 같은 외부 요인에 의한 자체발진특성의 열화를 방지하기 위하여 자동이득조절회로를 사용하였다. 진동형 각속도 검출 센서의 동작특성에 의하여 진폭변조 형태로 나타나는 각속도 신호를 검출하기 위하여 동기검파회로를 사용하였다. 동기검파회로에서는 반송파의 크기에 따라 검파신호의 크기가 달라지는 현상을 방지하기 위하여 스위칭 방식의 곱셈회로를 사용하였다. 설계된 칩은 0.5㎛ CMOS 공정으로 구현하였으며, 1.2㎜×1㎜의 칩 크기로 제작되었다. 실험 결과 3V의 전원전압에서 3.6mA의 전류를 소비하였으며, 칩과 각속도 센서를 결합한 정상동작상태에서 직류에서 50㎐까지 잡음 스펙트럼 밀도는 -95 dBrms/√㎐에서 -100 dBrms/√㎐ 사이에 존재하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.955-959
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• 2003

A technique for realizing linear phase IIR filters has been proposed by Powell-Chau which gives a real-time implementation of H(z-1).H(z), where H(z) is a causal nonlinear phase IIR filter. Powell-Chau system is linear but not timeinvariant system. Therefore, that system has group delay response that exhibits a minor sinusoidal variation superimposed on a constant value. In the signal processing, this oscillation seriously degrade the signal quality. Unfortunately, that system has a large sample delay of 4L and also more computational complexity. Proposed system is present a reduced computational complexity technique by moved the numerator polynomial of H(1/z) out to cascade with causal filter H(z) and remain only all-pole of H(1/z), then applied truncated infinite impulse response to finite with truncated IIR filtel $H_L$(z) and L sample delay to subtract the output sequence from the top and bottom filter. Proposed system is linear time invariance and group delay response and total harmonic distortion are also improved.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.611-614
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• 1991

In variable speed driving system of three phase induction motor controlled by an inverter, because of the switching of semiconductor devices in inverter, an appreciable amount of harmonic components of voltage waveform can cause the motor to generate losses, torque ripple, acoustic noise and oscillation of semiconductor devices. In this paper a new PAM type PWM inverter using IGBT is described. The output waveforms in the proposed PAM type PWM inverter are investigated both theoretiically and experimentally. The line-voltage waveform is composed of fundamental component and the sidebands of carrier frequency. The lower order harmonics are not included in the output wave form. As each inverter arm does not operate during two-thirds period, the heats, generated in the devices are reduced. That is, the size of the inverter system can he minimized because of the reduction in the heat dissipating equipment.

• 대한기계학회논문집
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• 제17권8호
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• pp.2122-2130
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• 1993

A numerical and experimental study has been performed on the flow in a shallow rectangular tank accompanying a vortex shedding. The model is composed of a rectangular tank with a vertical plate with a length half the width of the tank. The tank is subject to a horizontal sinusoidal oscillation. The numerical analysis shows that the pattern of vortex shedding changes considerably when the Reynolds number $R_e$ is varied from 500 to 7500. It is symmetric for $R_e$ <1500 and asymmetric for $R_e$ > 1500. The kinetic energies of the right-hand and left-hand sides of the vertical plate are used to quantify the degree of the asymmetry. Experimental visualization is carried out at $R_e$ = 3876 and 52000. The development of the streamline pattern at $R_e$ = 3876 is in closer agreement with the numerical result at $R_e$ = 1000 than that at $R_e$ =3876. The asymmetric pattern is observed at $R_e$ = 52000.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.