• Journal of Advanced Marine Engineering and Technology
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• v.38 no.1
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• pp.64-69
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• 2014

There are 440V and 220V electric source in ship. A 440V source is used to drive the power system such as crane and winch on deck and pump in engine room, and a 220V source is used to drive the power source for residential zones, control devices in engine room. In this paper, we made single phase inverter system for grid connection with 220V source for ship, and analyzed THD(Total harmonic distortion) by variation of parameters of L-C low pass filter and deadtime of inverter switching.

• Water for future
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• v.7 no.2
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• pp.83-91
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• 1974

On the constructions of fill type dams, usually the constructions materials is desired to be obtained in vicinity ofthe dam sitc to justify economical feasilblity of the project. In the stability analysis of the dams, core parts takesa small fraction of the slip circle and main function of core is to decrease dam permeability. This paper shows results of various tests as physical properties, compactions (using single, double triple and four times of the tandard compaction energy) and the permeability tests. Single decomposed granite and mixed materials with clay soils were used in this test. And conclusions of these tests are as follows; 1. Criteira of weathering ratio should be caleulated by density measarment. 2. Permeability coefficient maiuly depends on th #200 sieve passing, and also passing soil quantities depends on the weathering condition of the soil. 3. It was established that low weathered decomposed granite can not be used for the core materials of the fill type dams. On the other hand, moderately weathered decomposed granite soil with particles could pass through #200 sieve in a quantity over 10%, could chieve permeability in a magnitude of $1{\times}10^{-5} cm/see$. 4. With the decomposed granite soil it is possible to perform three times larger compaction energy than the standard energy without any problems.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2
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• pp.92-100
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• 1995

In this study, the bearing defects were modeled and the vibration of ball bearing faults was presented for the defective pattern. The vibration signal was measured for the single and multiple defected ball bearing at the various defect positions and rotation speed, and then the signal components using the HFRT(high frequency resonance technique) were analyzed by FFT. The experimental data analysis has shown that the frequencies generated in the single or multiple defected ball bearings appear with the characteristic defect frequency and harmonics of ball pass frequency peak. Signal processing by HFRT makes it possible not only to detect the presence of a defect but also to diagnose the defect part of the bearing.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.6
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• pp.447-452
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• 2008

In the paper, the product-type PLL system, which is so suitable for synchronizing a single phase grid voltage is designed. The PLL system is modelled with the small signal analysis. Both the cut-off frequency of low pass filter and the optimal gain are derived by considering the transient response for synchronization as well as a distortion of synchronization signal. Through the simulation studies and experimental results, the transient response and ripple component of synchronization signal are investigated with a variation of both the cut-off frequency and gain in order to verify the performance of design.

• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.606-613
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• 2010

This paper proposes a novel current-based maximum power point tracking (CMPPT) method for a single-phase photovoltaic power conditioning system (PV PCS) by using a modified incremental conductance method. The CMPPT method simplifies the entire control structure of the power conditioning system and uses an inherent current source characteristic of solar cell arrays. Therefore, it exhibits robust and fast response under a rapidly changing environmental condition. Digital phase locked loop technique using an all-pass filter is also introduced to detect the phase of grid voltage, as well as the peak voltage. Controllers of dc/dc boost converter, dc-link voltage, and dc/ac inverter are designed for coordinated operation. Furthermore, a current control using a pseudo synchronous d-q transformation is employed for grid current control with unity power factor. A 3 kW prototype PV PCS is built, and its experimental results are given to verify the effectiveness of the proposed control schemes.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.389-395
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• 2006

In the single-phase switched reluctance motor (SRM) drive, the required DC source is generally supplied by the circuit consisting of bridge rectifier with diodes and many filter capacitances connected with AC source. Although the peak torque ripple of SRM is small because of large capacity of the capacitance, the charge and discharge time swhich the AC source acts on the capacitance are small and the peak current will pass on the side of source, so power factor and system efficiency decrease. Therefore a novel SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor and switching topology. The proposed drive circuit consists of one switching part and diodes which can separate the output of AC/DC rectifier from the large capacitance and supply power to SRM alternately in order to realize reduction of torque ripple and improvement of power factor through the turn on and turn off of switching part. In addition, the validity of method is tested by simulation and experiment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.1
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• pp.211-215
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• 2017

The APF (All Pass Filter) method that utilizes the computational power of the controller is most commonly used. However, since the calculation of the filter coefficient is complicated, the calculation is carried out in advance. It is difficult to apply it to the frequency fluctuation environment because the coefficient value is fixed. In this paper, a new control method of single phase PLL that can be usefully used in PWM converter device for electric railway was explained. Comparison and examination of similarities and differences between the conventional APF method PLL controller method and the newly proposed modified MA filter method PLL technique were performed. The possibility of implementation of the modified MA filter method through computer simulation was analyzed. In conclusion, the method proposed as the conclusion was applied to the APU(Auxiliary Power System) of 8200 Series Electric Locomotive and its usefulness was confirmed.