• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1254-1258
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• 2004

This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

• 전기학회논문지P
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• 제52권1호
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• pp.20-27
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• 2003

In this study, we designed and made Ultrasonic motor-digital multi controller(USM-DMC) using FPGA chip, A54SX72A made in Actel Corporation. By the minute, USM-DMC can adjust the frequency, duty ratio, and phase difference parameters of USM by digital input to be each 11bit from PC. Therefore, when we use this controller, it is possible to apply typical three parameters individually as well as multi-parameters simultaneously to control the speed and the torque. What is more, the strongest point is that it can trace frequency based on optimized frequency as compared with the phase difference because we can input optimized resonant frequency while in motoring. And we test the speed of USM with the adjustment of multi-parameters, the phase difference-frequency. As the result of the test, in the case of the multi-parameters of the phase difference and frequency, the speed characteristic is more linear and stable, and wider in the range of control than the single-parameter of the phase difference or the frequency.

• Journal of Power Electronics
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• 제12권6호
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• 한국음향학회지
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• 제16권4호
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• pp.101-105
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• 1997

본 논문에서는 길이가 긴 덕트를 대상으로 개발된 능동소음제어 방법이 길이가 짧은 덕트에서 적용될 수 없는 문제점을 해결하기 위하여 음향 임피던스 0의 경계면에 의한 SISO(Single Input Single Output)알고리듬을 적용하였다. 하나의 마이크로폰으로 소음원의 입력과 에러 감지를 동시에 할 수 있는 SISO제어기는 TMS320E25 DSP(Digital Signal Processing)칩을 이용하여 실시간으로 구현하고 실험을 통하여 그 성능을 평가하였다. 길이가 0.80m인 짧은 덕트를 대상으로 실험한 결과 전체적으로 4.7dBA의 소음저감을 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.281-284
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• 2008

본 논문에서는 멀티미디어 SoC 플랫폼의 ASIC 설계에 대해 기술한다. 구현된 플랫폼은 32비트 OpenRISC1200 마이크로프로세서, WISHBONE 온 칩 버스, VGA 제어기, 디버그 인터페이스, SRAM 인터페이스 및 UART로 구성된다. 32 비트 OpenRISC1200 프로세서는 명령어 버스와 데이터 버스가 분리된 하버드 구조와 5단 파이프라인 구조를 가지고 VGA 제어기는 메모리로부터 읽은 이미지 파일에 대한 데이터를 RGB 값으로 CRT 혹은 LCD에 출력한다. 디버그 인터페이스는 플랫폼에 대한 디버깅 기능을 지원하고 SRAM 인터페이스는 18비트 어드레스 버스와 32비트 데이터 버스를 지원한다. UART는 RS232 프로토콜을 지원하는 시리얼 통신 기능을 제공한다. 본 플랫폼은 Xilinx VIRTEX-4 XC4VLX80 FPGA에 설계 및 검증되었다. 테스트 코드는 크로스 컴파일러로 생성되었고 JTAG 유틸리티 소프트웨어와 gdb를 이용하여 패러럴 케이블을 통해 FPGA 보드로 다운로드 하였다. 이 플랫폼은 최종적으로 Chartered 0.18um 공정을 이용하여 단일 ASIC 칩으로 구현 되었으며 100MHz 클록에서 동작함을 확인하였다.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• 전력전자학회논문지
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• 제12권5호
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• pp.355-363
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• 2007

본 논문에서는 무변압기형 3상 계통연계 PV PCS (photovoltaic power conditioning system)를 제안하였다. 태양전지의 국소 최대 전력점에서 발전하는 것을 방지하여 최대 전력점에서 발전을 하도록 개선한 P&O (perturb and observe) 방식의 MPPT (maximum power point tracking) 알고리즘을 제안하였다. 3상 전압형 인버터를 외부 직류 링크 전압제어기, 내부 전류제어기, 그리고 마이크로컨트롤러로 구현하기에 적합하도록 간단화한 공간벡터 변조법을 통해 제어하여 3상 계통연계 시 단위 역률을 실현하였다. 그리고 시스템의 안정성 향상과 역률 개선을 위해 직류 링크 전압을 더 빠르고 정확하게 제어하기 위한 알고리즘을 제안하였다. 모든 알고리즘과 제어기를 하나의 마이크로컨트롤러로 구현하고 제안된 알고리즘과 제어기의 우수성을 실험을 통해 검증하였다.

• ETRI Journal
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• 제37권6호
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• pp.1154-1164
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• 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a $0.18{\mu}m$ BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.600-602
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• 1996

The purpose of this paper is to develop a new maximum power point tracking(MPPT) using fuzzy set theory for air conditioning system. Fuzzy algorithm based on linguistic rules describing the operator's control strategy is applied to control step-up chopper for MPPT. Fuzzy algorithm is applied to control boost MPPT converter by temperature compensation effect with 8 bit single chip 8051 microcontroller. In this paper, temperature compensation(Becom Transducer : pf-T type) range is $-40^{\circ}C{\sim}+100^{\circ}C$.