• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• 한국전자통신학회논문지
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• 제13권4호
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• pp.721-728
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• 2018

본 논문은 다양한 구조의 선형 블록 오류정정코드를 소개하고, 이를 회로로 구현하여 비교 분석한 결과를 보여주고 있다. 메모리 시스템에서는 잡음 전력으로 인한 비트 오류를 방지하기 위해 ECC(: Error Correction Code)가 사용되어 왔다. ECC의 종류에는 SEC-DED(: Single Error Correction Double Error Detection)와 SEC-DED-DAEC(: Double Adjacent Error Correction)가 있다. SEC-DED인 Hsiao 코드와 SEC-DED-DAEC인 Dutta, Pedro 코드를 각각 Verilog HDL을 이용해 설계 후 $0.35{\mu}m$ CMOS 공정을 사용해 회로로 합성하였다. 시뮬레이션에 의하면 SEC-DED회로는 인접한 두 개의 비트 오류를 정정하지 못하지만 적은 회로 사용면적과 빠른 지연 시간의 장점이 있으며, SEC-DED-DAEC 회로의 경우 Pedro 코드와 Dutta 코드 간에는 면적, 지연 시간의 차이가 없으므로 오류 정정률이 개선된 Pedro 코드를 사용하는 것이 더 효율적임을 알 수 있다.

• 한국정보통신학회논문지
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• 제26권10호
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• 한국전자통신학회논문지
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• 제17권1호
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• pp.31-40
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• 2022

본 논문은 기존 QSBC(Quantum Short-Block Code)의 기능은 보전하면서 파울리 X 및 Y 오류에 의한 단일 비트플립 오류정정 기능을 부가한 증강된 QSBC를 제안한다. 증강된 QSBC는 기존 QSBC에 정보워드 수만큼의 추가적인 보조 큐비트와 Toffoli 게이트를 삽입해 단일 파울리 X 오류의 진단과 자동정정 기능을 부여한 것이다. 본 논문은 종자 벡터를 이용한 증강된 QSBC의 일반적 확장 방법과 확장성을 반영한 단일 비트플립오류 자동정정 함수의 Toffoli 게이트 실현 방법도 제시하였다. 본 논문이 제안한 증강된 QSBC는 보조 큐비트 삽입으로 인해 코딩률이 최소 1/3과 최대 1/2인 trade-off를 갖는다.

• 한국정보통신학회논문지
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• 제26권11호
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• 응용통계연구
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• 제29권1호
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• pp.75-83
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• 2016

본 연구에서는 금융시장 통합화에 따른 금융 시장 전염을 생물학적 전염개념에 기초하여 분석하는 검정 방법론을 제시하였다. 금융 시장 통합화를 측정하기 위하여 U-통계량을 사용하였고, 금융 시장 전염 검정을 위하여 단일방정식 오차수정 모형을 중심으로 잠재 요인모형, 분위수 회귀모형과 런검정을 사용하였다. 시뮬레이션결과 단일방정식 오차수정 모형이 자기상관을 갖는 오차항을 포함한 선형 회귀모형에서 비교적 높은 수준의 적합도를 일관성 있게 보여 주고 있다.

• 한국통신학회논문지
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• 제29권7A호
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• pp.712-718
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• 2004

분산형 라만 광증폭기와 어븀 첨가 광섬유 증폭기로 구성된 복합형 광증폭기를 사용하여 1.6 Tb/s (160${\times}$10 Gb/s) 전송 용량의 WDM 광신호를 단일 모드 광섬유 2,000 km에 전송한 결과에 대하여 기술한다. 복합형 광 증폭기를 사용하여 단일 모드 광섬유 2,000 km에 전송한 뒤의 평균 광 신호대 잡음비는 C/L-band에서 각각 20.5 dB, 21.9 dB 였고, 최저 Q-factor는 C/L-band에서 각각 14.65 dB(BER=5.8E-8), 13.75 dB(BER= 5.0E-7)였다. 이 결과에 Reed-Solomon (255, 239) Forward Error Correction(FEC) 코드 기능을 사용하여 무오류 전송 결과를 얻었다.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Journal of Positioning, Navigation, and Timing
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• 제12권2호
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• pp.121-128
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• 2023

When calculating the user's position using satellite signals, the signals originating from the satellite pass through the ionosphere and troposphere to the user. In particular, the ionosphere delay error that occurs when passing through the ionosphere delays when the signal is transmitted, generating a pseudorange error and position error at a large rate. Therefore, to improve position accuracy, it is essential to correct the ionosphere layer error. In a receiver capable of receiving dual frequency, the ionosphere error can be eliminated through a double difference, but in a single frequency receiver, an ionosphere correction model transmitted from a Global Navigation Satellite System (GNSS) satellite is used. The popularly used Klobuchar model is designed to improve performance globally. As such, it does not perform perfectly in the Korea region. In this paper, the characteristics of the delay in the ionosphere in the Korean region are identified through an analysis of 10 years of data, and an improved ionosphere correction model for the Korean region is presented using the widely employed Klobuchar model. Through the proposed model, vertical position error can be improved by up to 40% relative to the original Klobuchar model in the Korea region.

• ETRI Journal
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• 제30권6호
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• pp.799-806
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• 2008

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.