• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.12
• /
• pp.2503-2510
• /
• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.5
• /
• pp.1143-1150
• /
• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• Fisheries and Aquatic Sciences
• /
• v.5 no.3
• /
• pp.191-199
• /
• 2002

Pacific oysters Crassostrea gigas (Thunberg) were collected on April, 1999 and March­September, 2000 from Goseung Bay along the southern coast of Korea. The oysters tested cp;;ected from a depth of 0.5-2 m in which they cultured by a long line hanging method. The oxygen consumption rates (OCR) of oysters held under constant temperature and darkness (CC), were determined using an automatic intermittent-flow-respirometer (AIFR). Depending on holding periods after oyster collection, the experiments were divided into two groups: Group 7-d (held to ambient temperature for ca. 7 days) and Group 2l-d (held to ambient temperature for ca. 21 days). The OCR for Group 7-d single oyster displayed two peaks every day under CC, while Group 2l-d single oyster showed one peak every day. It is likely that the rhythmic patterns 02.6-12.8 hours) of the OCR in the Group 7-d single oyster may have been influenced by tidal currents at the sampling site. The rhythmic patterns (24.3-24.7 hours) in the Group 2l-d single oyster may have been shifted from two peaks to one peak each day under CC. The present study concludes that the OCR rhythm of wild oysters in nature is governed by two lunar-day clocks (24.8 hours); one driving one peak and the other driving the second peak. When oysters are subjected to the long-term CC conditions, one of the two-clock systems is depressed or only intermittently becomes active. Jpwever. the OCR rhythms by two to three oysters occurred arrhythmic patterns during the experiments and exhibited some evidence of weak rhythmicity of compared to those of a single oyster. It could be partly due to differences group effects.

• Journal of Photoscience
• /
• v.9 no.2
• /
• pp.9-12
• /
• 2002

Circadian rhythms can be seen in a variety of physiological functions in insects. Light is a powerful zeitgeber not only synchronizing but also modulating the rhythm to adjust insect's temporal structure to seasonal changes in the environmental cycle. There are two general effects of the length of light phase within 24 hr light cycles on the circadian rhythms, i.e., the modulation of free-running period and the waveform. Since the photoperiodic modulation of the free-running period is induced even in the clock mutant flies, per$\^$s/, the free-running period is not fully determined genetically. In crickets, the ratio of activity (a) and rest phase (p) under the constant darkness (DD) is clearly dependent on the photoperiod under which they have been kept. When experienced the longer photoperiod it becomes smaller. The magnitude of change in a/p-ratio is dependent on the number of cycles they experienced. The neuronal activity of the optic lobe in DD shows the a/p-ratio changing with the preceding photoperiod. These data suggest that a single circadian pacemaker stores and maintains the photoperiodic information and that there is a system that accumulates the effects of single photoperiod to cause greater effects.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.22-28
• /
• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.25-33
• /
• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.9 no.8
• /
• pp.3103-3120
• /
• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• Journal of Positioning, Navigation, and Timing
• /
• v.10 no.2
• /
• pp.75-82
• /
• 2021

Fields of high-precision positioning applications are growing fast across the mass market worldwide. Accordingly, the industry is focusing on developing methods of applying State-Space Representation (SSR) corrections on low-cost GNSS receivers. Among SSR correction types, this paper analyzes Safe Position Augmentation for Real Time Navigation (SPARTN) messages being offered by the SAfe and Precise CORrection DAta (SAPCORDA) company and validates positioning algorithms based on them. The first part of this paper introduces the SPARTN format in detail. Then, procedures on how to apply Basic-Precision Atmosphere Correction (BPAC) and High-Precision Atmosphere Correction (HPAC) messages are described. BPAC and HPAC messages are used for correcting satellite clock errors, satellite orbit errors, satellite signal biases and also ionospheric and tropospheric delays. Accuracies of positioning algorithms utilizing SPARTN messages were validated with two types of positioning strategies: Code-PPP using GPS pseudorange measurements and PPP-RTK including carrier phase measurements. In these performance checkups, only single-frequency measurements have been used and integer ambiguities were estimated as float numbers instead of fixed integers. The result shows that, with BPAC and HPAC corrections, the horizontal accuracy is 46% and 63% higher, respectively, compared to that obtained without application of SPARTN corrections. Also, the average horizontal and vertical RMSE values with HPAC are 17 cm and 27 cm, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.59-64
• /
• 2006

The slope of the ramp generator in a single slope ADC(analog-to-digital converter) suffers from process and frequency variation. This variation in ramp slope causes ADC gain variation and eventually limits the performance of the ISP(image signal processing) in a CIS(CMOS image sensor) that uses the single slope ADC. This paper proposes a ramp slope BISC(built-in-self-calibration) scheme for CIS. The CIS with proposed BISC was fabricated with a $0.35{\mu}m$ process. The measurement results show that the proposed architecture effectively calibrate the ramp slope against process and clock frequency variation. The silicon area overhead is less than $0.7\%$ of the full chip area.

• Structural Engineering and Mechanics
• /
• v.89 no.6
• /
• pp.589-599
• /
• 2024

This study presents the usability of the high-rate single-frequency Precise Point Positioning (SF-PPP) technique based on 20 Hz Global Positioning Systems (GPS)-only observations in detecting dynamic motions. SF-PPP solutions were obtained from post-mission and real-time GNSS corrections. These include the International GNSS Service (IGS)-Final, IGS real-time (RT), real-time MADOCA (Multi-GNSS Advanced Demonstration tool for Orbit and Clock Analysis), and real-time products from the Australian/New Zealand satellite-based augmentation systems (SBAS, known as SouthPAN). SF-PPP results were compared with LVDT (Linear Variable Differential Transformer) sensor and single-frequency relative positioning (SF-RP) solutions. The findings show that the SF-PPP technique successfully detects the harmonic motions, and the real-time products-based PPP solutions were as accurate as the final post-mission products. In the frequency domain, all GNSS-based methods evaluated in this contribution correctly detect the dominant frequency of short-term harmonic oscillations, while the differences in the amplitude values corresponding to the peak frequency do not exceed 1.1 mm. However, evaluations in the time domain show that SF-PPP needs high-pass filtering to detect accurate displacement since SF-PPP solutions include trends and low-frequency fluctuations, mainly due to atmospheric effects. Findings obtained in the time domain indicate that final, real-time, and MADOCA-based PPP results capture short-term dynamic behaviors with an accuracy ranging from 3.4 mm to 8.5 mm, and SBAS-based PPP solutions have several times higher RMSE values compared to other methods. However, after high-pass filtering, the accuracies obtained from PPP methods decreased to a few mm. The outcomes demonstrate the potential of the high-rate SF-PPP method to reliably monitor structural and earthquake-induced ground motions and vibration frequencies of structures.